168 lines
5.2 KiB
Plaintext
168 lines
5.2 KiB
Plaintext
Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
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===================================
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For some SoCs, the CPU frequency subset and voltage value of each OPP
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varies based on the silicon variant in use. Allwinner Process Voltage
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Scaling Tables defines the voltage and frequency value based on the
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speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
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reads the efuse value from the SoC to provide the OPP framework with
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required information.
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Required properties:
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--------------------
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In 'cpus' nodes:
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- operating-points-v2: Phandle to the operating-points-v2 table to use.
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In 'operating-points-v2' table:
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- compatible: Should be
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- 'allwinner,sun50i-h6-operating-points'.
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- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
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efuse registers that has information about the speedbin
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that is used to select the right frequency/voltage value
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pair. Please refer the for nvmem-cells bindings
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Documentation/devicetree/bindings/nvmem/nvmem.txt and
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also examples below.
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In every OPP node:
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- opp-microvolt-<name>: Voltage in micro Volts.
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At runtime, the platform can pick a <name> and
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matching opp-microvolt-<name> property.
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[See: opp.txt]
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HW: <name>:
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sun50i-h6 speed0 speed1 speed2
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Example 1:
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---------
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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};
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};
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cpu_opp_table: opp_table {
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compatible = "allwinner,sun50i-h6-operating-points";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp@480000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <480000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp@720000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp@816000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt-speed0 = <880000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp@888000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <888000000>;
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opp-microvolt-speed0 = <940000>;
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opp-microvolt-speed1 = <820000>;
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opp-microvolt-speed2 = <800000>;
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};
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opp@1080000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1080000000>;
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opp-microvolt-speed0 = <1060000>;
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opp-microvolt-speed1 = <880000>;
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opp-microvolt-speed2 = <840000>;
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};
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opp@1320000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt-speed0 = <1160000>;
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opp-microvolt-speed1 = <940000>;
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opp-microvolt-speed2 = <900000>;
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};
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opp@1488000000 {
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clock-latency-ns = <244144>; /* 8 32k periods */
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt-speed0 = <1160000>;
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opp-microvolt-speed1 = <1000000>;
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opp-microvolt-speed2 = <960000>;
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};
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};
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....
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soc {
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....
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sid: sid@3006000 {
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compatible = "allwinner,sun50i-h6-sid";
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reg = <0x03006000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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....
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speedbin_efuse: speed@1c {
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reg = <0x1c 4>;
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};
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};
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};
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