311 lines
6.6 KiB
Plaintext
311 lines
6.6 KiB
Plaintext
Mediatek MT7530 Ethernet switch
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================================
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Required properties:
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- compatible: may be compatible = "mediatek,mt7530"
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or compatible = "mediatek,mt7621"
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- #address-cells: Must be 1.
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- #size-cells: Must be 0.
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- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
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on multi-chip module belong to MT7623A has or the remotely standalone
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chip as the function MT7623N reference board provided for.
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If compatible mediatek,mt7530 is set then the following properties are required
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- core-supply: Phandle to the regulator node necessary for the core power.
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- io-supply: Phandle to the regulator node necessary for the I/O power.
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See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
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for details for the regulator setup on these boards.
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If the property mediatek,mcm isn't defined, following property is required
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- reset-gpios: Should be a gpio specifier for a reset line.
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Else, following properties are required
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- resets : Phandle pointing to the system reset controller with
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line index for the ethsys.
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- reset-names : Should be set to "mcm".
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Required properties for the child nodes within ports container:
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- reg: Port address described must be 6 for CPU port and from 0 to 5 for
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user ports.
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- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
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"cpu".
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Port 5 of the switch is muxed between:
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1. GMAC5: GMAC5 can interface with another external MAC or PHY.
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2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
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of the SOC. Used in many setups where port 0/4 becomes the WAN port.
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Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
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GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
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connected to external component!
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Port 5 modes/configurations:
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1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
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GMAC of the SOC.
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In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
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GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
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2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
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It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
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and RGMII delay.
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3. Port 5 is muxed to GMAC5 and can interface to an external phy.
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Port 5 becomes an extra switch port.
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Only works on platform where external phy TX<->RX lines are swapped.
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Like in the Ubiquiti ER-X-SFP.
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4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
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Currently a 2nd CPU port is not supported by DSA code.
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Depending on how the external PHY is wired:
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1. normal: The PHY can only connect to 2nd GMAC but not to the switch
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2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
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a ethernet port. But can't interface to the 2nd GMAC.
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Based on the DT the port 5 mode is configured.
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Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
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When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
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phy-mode must be set, see also example 2 below!
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* mt7621: phy-mode = "rgmii-txid";
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* mt7623: phy-mode = "rgmii";
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
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required, optional properties and how the integrated switch subnodes must
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be specified.
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Example:
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&mdio0 {
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switch@0 {
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compatible = "mediatek,mt7530";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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core-supply = <&mt6323_vpa_reg>;
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io-supply = <&mt6323_vemc3v3_reg>;
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reset-gpios = <&pio 33 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "wan";
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "trgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
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ð {
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "rgmii-txid";
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phy-handle = <&phy4>;
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Internal phy */
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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mt7530: switch@1f {
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compatible = "mediatek,mt7621";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1f>;
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pinctrl-names = "default";
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mediatek,mcm;
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resets = <&rstctrl 2>;
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reset-names = "mcm";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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/* Commented out. Port 4 is handled by 2nd GMAC.
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port@4 {
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reg = <4>;
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label = "lan4";
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};
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*/
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cpu_port0: port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
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ð {
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* External phy */
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ephy5: ethernet-phy@7 {
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reg = <7>;
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};
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mt7530: switch@1f {
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compatible = "mediatek,mt7621";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1f>;
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pinctrl-names = "default";
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mediatek,mcm;
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resets = <&rstctrl 2>;
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reset-names = "mcm";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan0";
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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};
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port@5 {
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reg = <5>;
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label = "lan5";
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phy-mode = "rgmii";
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phy-handle = <&ephy5>;
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};
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cpu_port0: port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "rgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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pause;
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};
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};
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};
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};
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};
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};
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