54 lines
1.9 KiB
Plaintext
54 lines
1.9 KiB
Plaintext
Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
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Required properties:
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- compatible : Should be "fsl,<processor>-flexcan"
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An implementation should also claim any of the following compatibles
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that it is fully backwards compatible with:
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- fsl,p1010-flexcan
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- reg : Offset and length of the register set for this device
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- interrupts : Interrupt tuple for this device
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Optional properties:
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- clock-frequency : The oscillator frequency driving the flexcan device
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- xceiver-supply: Regulator that powers the CAN transceiver
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- big-endian: This means the registers of FlexCAN controller are big endian.
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This is optional property.i.e. if this property is not present in
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device tree node then controller is assumed to be little endian.
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if this property is present then controller is assumed to be big
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endian.
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- fsl,stop-mode: register bits of stop mode control, the format is
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<&gpr req_gpr req_bit ack_gpr ack_bit>.
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gpr is the phandle to general purpose register node.
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req_gpr is the gpr register offset of CAN stop request.
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req_bit is the bit offset of CAN stop request.
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ack_gpr is the gpr register offset of CAN stop acknowledge.
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ack_bit is the bit offset of CAN stop acknowledge.
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- fsl,clk-source: Select the clock source to the CAN Protocol Engine (PE).
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It's SoC Implementation dependent. Refer to RM for detailed
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definition. If this property is not set in device tree node
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then driver selects clock source 1 by default.
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0: clock source 0 (oscillator clock)
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1: clock source 1 (peripheral clock)
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- wakeup-source: enable CAN remote wakeup
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Example:
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can@1c000 {
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compatible = "fsl,p1010-flexcan";
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reg = <0x1c000 0x1000>;
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interrupts = <48 0x2>;
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interrupt-parent = <&mpic>;
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clock-frequency = <200000000>; // filled in by bootloader
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fsl,clk-source = <0>; // select clock source 0 for PE
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};
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