61 lines
1.5 KiB
Plaintext
61 lines
1.5 KiB
Plaintext
Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs
|
|
|
|
This file documents the properties in addition to those available in
|
|
the MTD NAND bindings.
|
|
|
|
Required properties:
|
|
- compatible : contains one of:
|
|
- "amlogic,meson-gxl-nfc"
|
|
- "amlogic,meson-axg-nfc"
|
|
- clocks :
|
|
A list of phandle + clock-specifier pairs for the clocks listed
|
|
in clock-names.
|
|
|
|
- clock-names: Should contain the following:
|
|
"core" - NFC module gate clock
|
|
"device" - device clock from eMMC sub clock controller
|
|
"rx" - rx clock phase
|
|
"tx" - tx clock phase
|
|
|
|
- amlogic,mmc-syscon : Required for NAND clocks, it's shared with SD/eMMC
|
|
controller port C
|
|
|
|
Optional children nodes:
|
|
Children nodes represent the available nand chips.
|
|
|
|
Other properties:
|
|
see Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
|
|
|
|
Example demonstrate on AXG SoC:
|
|
|
|
sd_emmc_c_clkc: mmc@7000 {
|
|
compatible = "amlogic,meson-axg-mmc-clkc", "syscon";
|
|
reg = <0x0 0x7000 0x0 0x800>;
|
|
};
|
|
|
|
nand-controller@7800 {
|
|
compatible = "amlogic,meson-axg-nfc";
|
|
reg = <0x0 0x7800 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
clocks = <&clkc CLKID_SD_EMMC_C>,
|
|
<&sd_emmc_c_clkc CLKID_MMC_DIV>,
|
|
<&sd_emmc_c_clkc CLKID_MMC_PHASE_RX>,
|
|
<&sd_emmc_c_clkc CLKID_MMC_PHASE_TX>;
|
|
clock-names = "core", "device", "rx", "tx";
|
|
amlogic,mmc-syscon = <&sd_emmc_c_clkc>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_pins>;
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
nand-on-flash-bbt;
|
|
};
|
|
};
|