77 lines
2.8 KiB
Plaintext
77 lines
2.8 KiB
Plaintext
* Qualcomm SDHCI controller (sdhci-msm)
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This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci-msm driver.
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Required properties:
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- compatible: Should contain a SoC-specific string and a IP version string:
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version strings:
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"qcom,sdhci-msm-v4" for sdcc versions less than 5.0
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"qcom,sdhci-msm-v5" for sdcc version 5.0
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For SDCC version 5.0.0, MCI registers are removed from SDCC
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interface and some registers are moved to HC. New compatible
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string is added to support this change - "qcom,sdhci-msm-v5".
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full compatible strings with SoC and version:
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"qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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"qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
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"qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
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"qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
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NOTE that some old device tree files may be floating around that only
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have the string "qcom,sdhci-msm-v4" without the SoC compatible string
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but doing that should be considered a deprecated practice.
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- reg: Base address and length of the register in the following order:
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- Host controller register map (required)
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- SD Core register map (required for msm-v4 and below)
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- interrupts: Should contain an interrupt-specifiers for the interrupts:
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- Host controller interrupt (required)
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- pinctrl-names: Should contain only one value - "default".
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- pinctrl-0: Should specify pin control groups used for this controller.
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
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- clock-names: Should contain the following:
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"iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
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"core" - SDC MMC clock (MCLK) (required)
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"bus" - SDCC bus voter clock (optional)
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"xo" - TCXO clock (optional)
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"cal" - reference clock for RCLK delay calibration (optional)
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"sleep" - sleep clock for RCLK delay calibration (optional)
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Example:
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sdhc_1: sdhci@f9824900 {
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compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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interrupts = <0 123 0>;
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bus-width = <8>;
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non-removable;
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vmmc-supply = <&pm8941_l20>;
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vqmmc-supply = <&pm8941_s3>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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};
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sdhc_2: sdhci@f98a4900 {
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compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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interrupts = <0 125 0>;
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bus-width = <4>;
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cd-gpios = <&msmgpio 62 0x1>;
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vmmc-supply = <&pm8941_l21>;
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vqmmc-supply = <&pm8941_l13>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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};
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