157 lines
5.1 KiB
Plaintext
157 lines
5.1 KiB
Plaintext
FSI bus & engine generic device tree bindings
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=============================================
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The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
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engines within those slaves. However, we have a facility to match devicetree
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nodes to probed engines. This allows for fsi engines to expose non-probeable
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busses, which are then exposed by the device tree. For example, an FSI engine
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that is an I2C master - the I2C bus can be described by the device tree under
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the engine's device tree node.
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FSI masters may require their own DT nodes (to describe the master HW itself);
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that requirement is defined by the master's implementation, and is described by
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the fsi-master-* binding specifications.
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Under the masters' nodes, we can describe the bus topology using nodes to
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represent the FSI slaves and their slave engines. As a basic outline:
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fsi-master {
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/* top-level of FSI bus topology, bound to an FSI master driver and
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* exposes an FSI bus */
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fsi-slave@<link,id> {
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/* this node defines the FSI slave device, and is handled
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* entirely with FSI core code */
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fsi-slave-engine@<addr> {
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/* this node defines the engine endpoint & address range, which
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* is bound to the relevant fsi device driver */
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...
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};
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fsi-slave-engine@<addr> {
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...
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};
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};
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};
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Note that since the bus is probe-able, some (or all) of the topology may
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not be described; this binding only provides an optional facility for
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adding subordinate device tree nodes as children of FSI engines.
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FSI masters
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-----------
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FSI master nodes declare themselves as such with the "fsi-master" compatible
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value. It's likely that an implementation-specific compatible value will
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be needed as well, for example:
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compatible = "fsi-master-gpio", "fsi-master";
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Since the master nodes describe the top-level of the FSI topology, they also
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need to declare the FSI-standard addressing scheme. This requires two cells for
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addresses (link index and slave ID), and no size:
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#address-cells = <2>;
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#size-cells = <0>;
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An optional boolean property can be added to indicate that a particular master
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should not scan for connected devices at initialization time. This is
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necessary in cases where a scan could cause arbitration issues with other
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masters that may be present on the bus.
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no-scan-on-init;
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FSI slaves
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----------
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Slaves are identified by a (link-index, slave-id) pair, so require two cells
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for an address identifier. Since these are not a range, no size cells are
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required. For an example, a slave on link 1, with ID 2, could be represented
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as:
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cfam@1,2 {
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reg = <1 2>;
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[...];
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}
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Each slave provides an address-space, under which the engines are accessible.
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That address space has a maximum of 23 bits, so we use one cell to represent
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addresses and sizes in the slave address space:
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#address-cells = <1>;
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#size-cells = <1>;
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Optionally, a slave can provide a global unique chip ID which is used to
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identify the physical location of the chip in a system specific way
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chip-id = <0>;
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FSI engines (devices)
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---------------------
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Engines are identified by their address under the slaves' address spaces. We
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use a single cell for address and size. Engine nodes represent the endpoint
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FSI device, and are passed to those FSI device drivers' ->probe() functions.
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For example, for a slave using a single 0x400-byte page starting at address
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0xc00:
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engine@c00 {
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reg = <0xc00 0x400>;
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};
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Full example
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------------
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Here's an example that illustrates:
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- an FSI master
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- connected to an FSI slave
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- that contains an engine that is an I2C master
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- connected to an I2C EEPROM
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The FSI master may be connected to additional slaves, and slaves may have
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additional engines, but they don't necessarily need to be describe in the
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device tree if no extra platform information is required.
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/* The GPIO-based FSI master node, describing the top level of the
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* FSI bus
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*/
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gpio-fsi {
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compatible = "fsi-master-gpio", "fsi-master";
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#address-cells = <2>;
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#size-cells = <0>;
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/* A FSI slave (aka. CFAM) at link 0, ID 0. */
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cfam@0,0 {
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reg = <0 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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chip-id = <0>;
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/* FSI engine at 0xc00, using a single page. In this example,
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* it's an I2C master controller, so subnodes describe the
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* I2C bus.
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*/
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i2c-controller@c00 {
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reg = <0xc00 0x400>;
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/* Engine-specific data. In this case, we're describing an
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* I2C bus, so we're conforming to the generic I2C binding
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*/
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compatible = "some-vendor,fsi-i2c-controller";
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#address-cells = <1>;
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#size-cells = <1>;
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/* I2C endpoint device: an Atmel EEPROM */
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eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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pagesize = <64>;
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};
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};
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};
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};
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