40 lines
1.4 KiB
Plaintext
40 lines
1.4 KiB
Plaintext
Synopsys DesignWare AXI DMA Controller
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Required properties:
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- compatible: "snps,axi-dma-1.01a"
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- reg: Address range of the DMAC registers. This should include
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all of the per-channel registers.
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- interrupt: Should contain the DMAC interrupt number.
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- dma-channels: Number of channels supported by hardware.
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- snps,dma-masters: Number of AXI masters supported by the hardware.
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- snps,data-width: Maximum AXI data width supported by hardware.
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(0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
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- snps,priority: Priority of channel. Array size is equal to the number of
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dma-channels. Priority value must be programmed within [0:dma-channels-1]
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range. (0 - minimum priority)
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- snps,block-size: Maximum block size supported by the controller channel.
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Array size is equal to the number of dma-channels.
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Optional properties:
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- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
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in this property. If this property is missing the maximum AXI burst length
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supported by DMAC is used. [1:256]
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Example:
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dmac: dma-controller@80000 {
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compatible = "snps,axi-dma-1.01a";
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reg = <0x80000 0x400>;
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clocks = <&core_clk>, <&cfgr_clk>;
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clock-names = "core-clk", "cfgr-clk";
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interrupt-parent = <&intc>;
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interrupts = <27>;
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dma-channels = <4>;
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snps,dma-masters = <2>;
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snps,data-width = <3>;
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snps,block-size = <4096 4096 4096 4096>;
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snps,priority = <0 1 2 3>;
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snps,axi-max-burst-len = <16>;
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};
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