142 lines
4.5 KiB
Plaintext
142 lines
4.5 KiB
Plaintext
Qualcomm Technologies, Inc. DPU KMS
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Description:
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Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc.
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The DPU display controller is found in SDM845 SoC.
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MDSS:
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Required properties:
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- compatible: "qcom,sdm845-mdss"
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- reg: physical base address and length of contoller's registers.
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- reg-names: register region names. The following region is required:
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* "mdss"
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- power-domains: a power domain consumer specifier according to
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Documentation/devicetree/bindings/power/power_domain.txt
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- clocks: list of clock specifiers for clocks needed by the device.
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- clock-names: device clock names, must be in same order as clocks property.
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The following clocks are required:
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* "iface"
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* "bus"
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* "core"
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- interrupts: interrupt signal from MDSS.
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- interrupt-controller: identifies the node as an interrupt controller.
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- iommus: phandle of iommu device node.
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- #address-cells: number of address cells for the MDSS children. Should be 1.
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- #size-cells: Should be 1.
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- ranges: parent bus address space is the same as the child bus address space.
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- interconnects : interconnect path specifier for MDSS according to
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Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
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2 paths corresponding to 2 AXI ports.
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- interconnect-names : MDSS will have 2 port names to differentiate between the
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2 interconnect paths defined with interconnect specifier.
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Optional properties:
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- assigned-clocks: list of clock specifiers for clocks needing rate assignment
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- assigned-clock-rates: list of clock frequencies sorted in the same order as
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the assigned-clocks property.
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MDP:
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Required properties:
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- compatible: "qcom,sdm845-dpu"
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- reg: physical base address and length of controller's registers.
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- reg-names : register region names. The following region is required:
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* "mdp"
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* "vbif"
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- clocks: list of clock specifiers for clocks needed by the device.
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- clock-names: device clock names, must be in same order as clocks property.
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The following clocks are required.
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* "bus"
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* "iface"
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* "core"
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* "vsync"
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- interrupts: interrupt line from DPU to MDSS.
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- ports: contains the list of output ports from DPU device. These ports connect
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to interfaces that are external to the DPU hardware, such as DSI, DP etc.
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Each output port contains an endpoint that describes how it is connected to an
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external interface. These are described by the standard properties documented
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here:
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Documentation/devicetree/bindings/graph.txt
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Documentation/devicetree/bindings/media/video-interfaces.txt
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Port 0 -> DPU_INTF1 (DSI1)
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Port 1 -> DPU_INTF2 (DSI2)
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Optional properties:
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- assigned-clocks: list of clock specifiers for clocks needing rate assignment
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- assigned-clock-rates: list of clock frequencies sorted in the same order as
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the assigned-clocks property.
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Example:
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mdss: mdss@ae00000 {
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compatible = "qcom,sdm845-mdss";
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reg = <0xae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&clock_dispcc 0>;
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clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
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<&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "bus", "core";
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assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
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assigned-clock-rates = <300000000>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
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<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
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interconnect-names = "mdp0-mem", "mdp1-mem";
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iommus = <&apps_iommu 0>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xae00000 0xb2008>;
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mdss_mdp: mdp@ae01000 {
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compatible = "qcom,sdm845-dpu";
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reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
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<&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
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<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
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<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "iface", "bus", "core", "vsync";
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assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
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<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
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assigned-clock-rates = <0 0 300000000 19200000>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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};
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};
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