67 lines
1.9 KiB
Plaintext
67 lines
1.9 KiB
Plaintext
Thine Electronics THC63LVD1024 LVDS decoder
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The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams
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to parallel data outputs. The chip supports single/dual input/output modes,
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handling up to two LVDS input streams and up to two digital CMOS/TTL outputs.
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Single or dual operation mode, output data mapping and DDR output modes are
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configured through input signals and the chip does not expose any control bus.
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Required properties:
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- compatible: Shall be "thine,thc63lvd1024"
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- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input,
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PPL and digital circuitry
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Optional properties:
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- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low
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- oe-gpios: Output enable GPIO signal, pin name "OE". Active high
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The THC63LVD1024 video port connections are modeled according
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to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt
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Required video port nodes:
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- port@0: First LVDS input port
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- port@2: First digital CMOS/TTL parallel output
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Optional video port nodes:
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- port@1: Second LVDS input port
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- port@3: Second digital CMOS/TTL parallel output
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The device can operate in single-link mode or dual-link mode. In single-link
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mode, all pixels are received on port@0, and port@1 shall not contain any
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endpoint. In dual-link mode, even-numbered pixels are received on port@0 and
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odd-numbered pixels on port@1, and both port@0 and port@1 shall contain
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endpoints.
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Example:
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--------
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thc63lvd1024: lvds-decoder {
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compatible = "thine,thc63lvd1024";
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vcc-supply = <®_lvds_vcc>;
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powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lvds_dec_in_0: endpoint {
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remote-endpoint = <&lvds_out>;
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};
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};
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port@2{
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reg = <2>;
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lvds_dec_out_2: endpoint {
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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