139 lines
4.8 KiB
Plaintext
139 lines
4.8 KiB
Plaintext
Texas Instruments sysc interconnect target module wrapper binding
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Texas Instruments SoCs can have a generic interconnect target module
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hardware for devices connected to various interconnects such as L3
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interconnect (Arteris NoC) and L4 interconnect (Sonics s3220). The sysc
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is mostly used for interaction between module and PRCM. It participates
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in the OCP Disconnect Protocol but other than that is mostly independent
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of the interconnect.
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Each interconnect target module can have one or more devices connected to
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it. There is a set of control registers for managing interconnect target
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module clocks, idle modes and interconnect level resets for the module.
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These control registers are sprinkled into the unused register address
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space of the first child device IP block managed by the interconnect
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target module and typically are named REVISION, SYSCONFIG and SYSSTATUS.
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Required standard properties:
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- compatible shall be one of the following generic types:
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"ti,sysc"
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"ti,sysc-omap2"
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"ti,sysc-omap4"
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"ti,sysc-omap4-simple"
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or one of the following derivative types for hardware
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needing special workarounds:
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"ti,sysc-omap2-timer"
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"ti,sysc-omap4-timer"
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"ti,sysc-omap3430-sr"
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"ti,sysc-omap3630-sr"
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"ti,sysc-omap4-sr"
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"ti,sysc-omap3-sham"
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"ti,sysc-omap-aes"
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"ti,sysc-mcasp"
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"ti,sysc-dra7-mcasp"
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"ti,sysc-usb-host-fs"
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"ti,sysc-dra7-mcan"
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- reg shall have register areas implemented for the interconnect
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target module in question such as revision, sysc and syss
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- reg-names shall contain the register names implemented for the
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interconnect target module in question such as
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"rev, "sysc", and "syss"
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- ranges shall contain the interconnect target module IO range
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available for one or more child device IP blocks managed
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by the interconnect target module, the ranges may include
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multiple ranges such as device L4 range for control and
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parent L3 range for DMA access
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Optional properties:
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- ti,sysc-mask shall contain mask of supported register bits for the
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SYSCONFIG register as documented in the Technical Reference
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Manual (TRM) for the interconnect target module
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- ti,sysc-midle list of master idle modes supported by the interconnect
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target module as documented in the TRM for SYSCONFIG
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register MIDLEMODE bits
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- ti,sysc-sidle list of slave idle modes supported by the interconnect
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target module as documented in the TRM for SYSCONFIG
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register SIDLEMODE bits
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- ti,sysc-delay-us delay needed after OCP softreset before accssing
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SYSCONFIG register again
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- ti,syss-mask optional mask of reset done status bits as described in the
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TRM for SYSSTATUS registers, typically 1 with some devices
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having separate reset done bits for children like OHCI and
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EHCI
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- clocks clock specifier for each name in the clock-names as
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specified in the binding documentation for ti-clkctrl,
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typically available for all interconnect targets on TI SoCs
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based on omap4 except if it's read-only register in hwauto
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mode as for example omap4 L4_CFG_CLKCTRL
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- clock-names should contain at least "fck", and optionally also "ick"
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depending on the SoC and the interconnect target module,
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some interconnect target modules also need additional
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optional clocks that can be specified as listed in TRM
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for the related CLKCTRL register bits 8 to 15 such as
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"dbclk" or "clk32k" depending on their role
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- ti,hwmods optional TI interconnect module name to use legacy
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hwmod platform data
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- ti,no-reset-on-init interconnect target module should not be reset at init
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- ti,no-idle-on-init interconnect target module should not be idled at init
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- ti,no-idle interconnect target module should not be idled
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Example: Single instance of MUSB controller on omap4 using interconnect ranges
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using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
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target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
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compatible = "ti,sysc-omap2";
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ti,hwmods = "usb_otg_hs";
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reg = <0x2b400 0x4>,
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<0x2b404 0x4>,
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<0x2b408 0x4>;
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reg-names = "rev", "sysc", "syss";
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clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
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clock-names = "fck";
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ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2b000 0x1000>;
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usb_otg_hs: otg@0 {
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compatible = "ti,omap4-musb";
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reg = <0x0 0x7ff>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy>;
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...
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};
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};
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Note that other SoCs, such as am335x can have multiple child devices. On am335x
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there are two MUSB instances, two USB PHY instances, and a single CPPI41 DMA
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instance as children of a single interconnect target module.
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