38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
ML-AHB interconnect bindings
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These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
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a Cortex-M subsystem with dedicated memories.
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The MCU SRAM and RETRAM memory parts can be accessed through different addresses
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(see "RAM aliases" in [1]) using different buses (see [2]) : balancing the
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Cortex-M firmware accesses among those ports allows to tune the system
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performance.
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[1]: https://www.st.com/resource/en/reference_manual/dm00327659.pdf
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[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
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Required properties:
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- compatible: should be "simple-bus"
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- dma-ranges: describes memory addresses translation between the local CPU and
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the remote Cortex-M processor. Each memory region, is declared with
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3 parameters:
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- param 1: device base address (Cortex-M processor address)
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- param 2: physical base address (local CPU address)
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- param 3: size of the memory region.
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The Cortex-M remote processor accessed via the mlahb interconnect is described
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by a child node.
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Example:
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mlahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x00000000 0x38000000 0x10000>,
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<0x10000000 0x10000000 0x60000>,
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<0x30000000 0x30000000 0x60000>;
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m4_rproc: m4@10000000 {
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...
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};
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};
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