173 lines
4.3 KiB
C
173 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* IMX pinmux core definitions
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*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro Ltd.
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*
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* Author: Dong Aisheng <dong.aisheng@linaro.org>
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*/
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#ifndef __DRIVERS_PINCTRL_IMX_H
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#define __DRIVERS_PINCTRL_IMX_H
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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struct platform_device;
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extern struct pinmux_ops imx_pmx_ops;
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extern const struct dev_pm_ops imx_pinctrl_pm_ops;
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/**
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* struct imx_pin_mmio - MMIO pin configurations
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* @mux_mode: the mux mode for this pin.
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* @input_reg: the select input register offset for this pin if any
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* 0 if no select input setting needed.
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* @input_val: the select input value for this pin.
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* @configs: the config for this pin.
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*/
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struct imx_pin_mmio {
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unsigned int mux_mode;
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u16 input_reg;
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unsigned int input_val;
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unsigned long config;
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};
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/**
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* struct imx_pin_scu - SCU pin configurations
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* @mux: the mux mode for this pin.
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* @configs: the config for this pin.
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*/
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struct imx_pin_scu {
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unsigned int mux_mode;
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unsigned long config;
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};
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/**
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* struct imx_pin - describes a single i.MX pin
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* @pin: the pin_id of this pin
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* @conf: config type of this pin, either mmio or scu
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*/
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struct imx_pin {
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unsigned int pin;
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union {
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struct imx_pin_mmio mmio;
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struct imx_pin_scu scu;
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} conf;
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};
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/**
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* struct imx_pin_reg - describe a pin reg map
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* @mux_reg: mux register offset
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* @conf_reg: config register offset
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*/
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struct imx_pin_reg {
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s16 mux_reg;
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s16 conf_reg;
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};
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/* decode a generic config into raw register value */
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struct imx_cfg_params_decode {
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enum pin_config_param param;
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u32 mask;
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u8 shift;
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bool invert;
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};
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struct imx_pinctrl_soc_info {
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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unsigned int flags;
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const char *gpr_compatible;
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/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
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unsigned int mux_mask;
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u8 mux_shift;
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/* generic pinconf */
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bool generic_pinconf;
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const struct pinconf_generic_params *custom_params;
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unsigned int num_custom_params;
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const struct imx_cfg_params_decode *decodes;
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unsigned int num_decodes;
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void (*fixup)(unsigned long *configs, unsigned int num_configs,
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u32 *raw_config);
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int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset,
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bool input);
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};
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/**
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* @dev: a pointer back to containing device
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* @base: the offset to the controller in virtual memory
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*/
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struct imx_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctl;
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void __iomem *base;
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void __iomem *input_sel_base;
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const struct imx_pinctrl_soc_info *info;
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struct imx_pin_reg *pin_regs;
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unsigned int group_index;
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struct mutex mutex;
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};
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#define IMX_CFG_PARAMS_DECODE(p, m, o) \
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{ .param = p, .mask = m, .shift = o, .invert = false, }
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#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
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{ .param = p, .mask = m, .shift = o, .invert = true, }
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#define SHARE_MUX_CONF_REG BIT(0)
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#define ZERO_OFFSET_VALID BIT(1)
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#define IMX_USE_SCU BIT(2)
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#define NO_MUX 0x0
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#define NO_PAD 0x0
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#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
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#define PAD_CTL_MASK(len) ((1 << len) - 1)
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#define IMX_MUX_MASK 0x7
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#define IOMUXC_CONFIG_SION (0x1 << 4)
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int imx_pinctrl_probe(struct platform_device *pdev,
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const struct imx_pinctrl_soc_info *info);
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#ifdef CONFIG_PINCTRL_IMX_SCU
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#define BM_PAD_CTL_GP_ENABLE BIT(30)
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#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
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#define BP_PAD_CTL_IFMUX 27
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int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
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int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
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unsigned long *config);
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int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
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unsigned long *configs, unsigned num_configs);
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void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
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unsigned int *pin_id, struct imx_pin *pin,
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const __be32 **list_p);
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#else
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static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
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unsigned pin_id, unsigned long *config)
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{
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return -EINVAL;
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}
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static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
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unsigned pin_id, unsigned long *configs,
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unsigned num_configs)
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{
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return -EINVAL;
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}
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static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
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unsigned int *pin_id,
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struct imx_pin *pin,
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const __be32 **list_p)
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{
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}
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#endif
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#endif /* __DRIVERS_PINCTRL_IMX_H */
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