366 lines
11 KiB
C
366 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DMA support for Internal DMAC with SDHI SD/SDIO controller
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*
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* Copyright (C) 2016-19 Renesas Electronics Corporation
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* Copyright (C) 2016-17 Horms Solutions, Simon Horman
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* Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/host.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/pagemap.h>
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#include <linux/scatterlist.h>
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#include <linux/sys_soc.h>
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#include "renesas_sdhi.h"
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#include "tmio_mmc.h"
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#define DM_CM_DTRAN_MODE 0x820
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#define DM_CM_DTRAN_CTRL 0x828
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#define DM_CM_RST 0x830
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#define DM_CM_INFO1 0x840
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#define DM_CM_INFO1_MASK 0x848
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#define DM_CM_INFO2 0x850
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#define DM_CM_INFO2_MASK 0x858
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#define DM_DTRAN_ADDR 0x880
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/* DM_CM_DTRAN_MODE */
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#define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */
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#define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */
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#define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4))
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#define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */
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/* DM_CM_DTRAN_CTRL */
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#define DTRAN_CTRL_DM_START BIT(0)
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/* DM_CM_RST */
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#define RST_DTRANRST1 BIT(9)
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#define RST_DTRANRST0 BIT(8)
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#define RST_RESERVED_BITS GENMASK_ULL(31, 0)
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/* DM_CM_INFO1 and DM_CM_INFO1_MASK */
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#define INFO1_CLEAR 0
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#define INFO1_MASK_CLEAR GENMASK_ULL(31, 0)
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#define INFO1_DTRANEND1 BIT(17)
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#define INFO1_DTRANEND0 BIT(16)
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/* DM_CM_INFO2 and DM_CM_INFO2_MASK */
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#define INFO2_MASK_CLEAR GENMASK_ULL(31, 0)
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#define INFO2_DTRANERR1 BIT(17)
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#define INFO2_DTRANERR0 BIT(16)
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/*
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* Specification of this driver:
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* - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
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* - Since this SDHI DMAC register set has 16 but 32-bit width, we
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* need a custom accessor.
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*/
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static unsigned long global_flags;
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/*
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* Workaround for avoiding to use RX DMAC by multiple channels.
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* On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
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* RX DMAC simultaneously, sometimes hundreds of bytes data are not
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* stored into the system memory even if the DMAC interrupt happened.
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* So, this driver then uses one RX DMAC channel only.
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*/
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#define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0
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#define SDHI_INTERNAL_DMAC_RX_IN_USE 1
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/* RZ/A2 does not have the ADRR_MODE bit */
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#define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
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/* Definitions for sampling clocks */
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static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
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{
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.clk_rate = 0,
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.tap = 0x00000300,
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.tap_hs400 = 0x00000704,
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},
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};
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static const struct renesas_sdhi_of_data of_rza2_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY,
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.tmio_ocr_mask = MMC_VDD_32_33,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23,
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.bus_shift = 2,
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.scc_offset = 0 - 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* DMAC can handle 32bit blk count but only 1 segment */
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.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
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.max_segs = 1,
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};
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static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
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TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
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.capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
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MMC_CAP_CMD23,
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.capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
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.bus_shift = 2,
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.scc_offset = 0x1000,
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.taps = rcar_gen3_scc_taps,
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.taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
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/* DMAC can handle 32bit blk count but only 1 segment */
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.max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE,
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.max_segs = 1,
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};
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static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
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{ .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
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{ .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
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{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
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{},
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};
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MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
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static void
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renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
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int addr, u64 val)
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{
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writeq(val, host->ctl + addr);
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}
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static void
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renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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if (!host->chan_tx || !host->chan_rx)
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return;
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if (!enable)
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
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INFO1_CLEAR);
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if (priv->dma_priv.enable)
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priv->dma_priv.enable(host, enable);
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}
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static void
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renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
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u64 val = RST_DTRANRST1 | RST_DTRANRST0;
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
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RST_RESERVED_BITS & ~val);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
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RST_RESERVED_BITS | val);
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clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
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renesas_sdhi_internal_dmac_enable_dma(host, true);
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}
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static void
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renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
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struct renesas_sdhi *priv = host_to_priv(host);
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tasklet_schedule(&priv->dma_priv.dma_complete);
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}
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static void
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renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
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struct mmc_data *data)
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{
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struct scatterlist *sg = host->sg_ptr;
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u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
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if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags))
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dtran_mode |= DTRAN_MODE_ADDR_MODE;
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if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
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mmc_get_dma_dir(data)))
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goto force_pio;
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/* This DMAC cannot handle if buffer is not 8-bytes alignment */
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if (!IS_ALIGNED(sg_dma_address(sg), 8))
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goto force_pio_with_unmap;
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if (data->flags & MMC_DATA_READ) {
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dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
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if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
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test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
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goto force_pio_with_unmap;
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} else {
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dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
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}
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renesas_sdhi_internal_dmac_enable_dma(host, true);
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/* set dma parameters */
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
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dtran_mode);
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renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
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sg_dma_address(sg));
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host->dma_on = true;
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return;
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force_pio_with_unmap:
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dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
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force_pio:
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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}
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static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
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{
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struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
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tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
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/* start the DMAC */
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
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DTRAN_CTRL_DM_START);
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}
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static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
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{
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struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
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enum dma_data_direction dir;
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spin_lock_irq(&host->lock);
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if (!host->data)
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goto out;
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if (host->data->flags & MMC_DATA_READ)
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dir = DMA_FROM_DEVICE;
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else
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dir = DMA_TO_DEVICE;
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renesas_sdhi_internal_dmac_enable_dma(host, false);
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dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
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if (dir == DMA_FROM_DEVICE)
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clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
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tmio_mmc_do_data_irq(host);
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out:
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spin_unlock_irq(&host->lock);
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}
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static void
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renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
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struct tmio_mmc_data *pdata)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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/* Disable DMAC interrupts, we don't use them */
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
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INFO1_MASK_CLEAR);
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renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
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INFO2_MASK_CLEAR);
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/* Each value is set to non-zero to assume "enabling" each DMA */
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host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
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tasklet_init(&priv->dma_priv.dma_complete,
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renesas_sdhi_internal_dmac_complete_tasklet_fn,
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(unsigned long)host);
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tasklet_init(&host->dma_issue,
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renesas_sdhi_internal_dmac_issue_tasklet_fn,
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(unsigned long)host);
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}
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static void
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renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
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{
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/* Each value is set to zero to assume "disabling" each DMA */
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host->chan_rx = host->chan_tx = NULL;
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}
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static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
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.start = renesas_sdhi_internal_dmac_start_dma,
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.enable = renesas_sdhi_internal_dmac_enable_dma,
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.request = renesas_sdhi_internal_dmac_request_dma,
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.release = renesas_sdhi_internal_dmac_release_dma,
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.abort = renesas_sdhi_internal_dmac_abort_dma,
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.dataend = renesas_sdhi_internal_dmac_dataend_dma,
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};
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/*
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* Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
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* implementation as others may use a different implementation.
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*/
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static const struct soc_device_attribute soc_whitelist[] = {
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/* specific ones */
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{ .soc_id = "r7s9210",
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.data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
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{ .soc_id = "r8a7795", .revision = "ES1.*",
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.data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
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{ .soc_id = "r8a7796", .revision = "ES1.0",
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.data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
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/* generic ones */
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{ .soc_id = "r8a774a1" },
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{ .soc_id = "r8a774c0" },
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{ .soc_id = "r8a77470" },
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{ .soc_id = "r8a7795" },
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{ .soc_id = "r8a7796" },
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{ .soc_id = "r8a77965" },
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{ .soc_id = "r8a77970" },
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{ .soc_id = "r8a77980" },
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{ .soc_id = "r8a77990" },
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{ .soc_id = "r8a77995" },
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{ /* sentinel */ }
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};
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static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
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{
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const struct soc_device_attribute *soc = soc_device_match(soc_whitelist);
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struct device *dev = &pdev->dev;
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if (!soc)
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return -ENODEV;
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global_flags |= (unsigned long)soc->data;
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dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
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if (!dev->dma_parms)
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return -ENOMEM;
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/* value is max of SD_SECCNT. Confirmed by HW engineers */
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dma_set_max_seg_size(dev, 0xffffffff);
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return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
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}
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static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
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pm_runtime_force_resume)
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SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
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tmio_mmc_host_runtime_resume,
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NULL)
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};
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static struct platform_driver renesas_internal_dmac_sdhi_driver = {
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.driver = {
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.name = "renesas_sdhi_internal_dmac",
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.pm = &renesas_sdhi_internal_dmac_dev_pm_ops,
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.of_match_table = renesas_sdhi_internal_dmac_of_match,
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},
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.probe = renesas_sdhi_internal_dmac_probe,
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.remove = renesas_sdhi_remove,
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};
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module_platform_driver(renesas_internal_dmac_sdhi_driver);
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MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
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MODULE_AUTHOR("Yoshihiro Shimoda");
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MODULE_LICENSE("GPL v2");
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