511 lines
17 KiB
C
511 lines
17 KiB
C
/*
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* Copyright (C) 2013 Broadcom Corporation
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* Copyright 2013 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CLK_KONA_H
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#define _CLK_KONA_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/clk-provider.h>
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#define BILLION 1000000000
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/* The common clock framework uses u8 to represent a parent index */
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#define PARENT_COUNT_MAX ((u32)U8_MAX)
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#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
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#define BAD_CLK_NAME ((const char *)-1)
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#define BAD_SCALED_DIV_VALUE U64_MAX
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/*
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* Utility macros for object flag management. If possible, flags
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* should be defined such that 0 is the desired default value.
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*/
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#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
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#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
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#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
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#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
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#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
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/* CCU field state tests */
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#define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
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/* Clock field state tests */
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#define policy_exists(policy) ((policy)->offset != 0)
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#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
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#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
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#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
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#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
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#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
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#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
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#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
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#define hyst_exists(hyst) ((hyst)->offset != 0)
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#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
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#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
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#define divider_has_fraction(div) (!divider_is_fixed(div) && \
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(div)->u.s.frac_width > 0)
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#define selector_exists(sel) ((sel)->width != 0)
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#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
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#define policy_lvm_en_exists(enable) ((enable)->offset != 0)
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#define policy_ctl_exists(control) ((control)->offset != 0)
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/* Clock type, used to tell common block what it's part of */
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enum bcm_clk_type {
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bcm_clk_none, /* undefined clock type */
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bcm_clk_bus,
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bcm_clk_core,
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bcm_clk_peri
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};
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/*
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* CCU policy control for clocks. Clocks can be enabled or disabled
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* based on the CCU policy in effect. One bit in each policy mask
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* register (one per CCU policy) represents whether the clock is
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* enabled when that policy is effect or not. The CCU policy engine
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* must be stopped to update these bits, and must be restarted again
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* afterward.
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*/
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struct bcm_clk_policy {
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u32 offset; /* first policy mask register offset */
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u32 bit; /* bit used in all mask registers */
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};
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/* Policy initialization macro */
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#define POLICY(_offset, _bit) \
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{ \
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.offset = (_offset), \
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.bit = (_bit), \
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}
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/*
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* Gating control and status is managed by a 32-bit gate register.
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*
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* There are several types of gating available:
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* - (no gate)
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* A clock with no gate is assumed to be always enabled.
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* - hardware-only gating (auto-gating)
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* Enabling or disabling clocks with this type of gate is
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* managed automatically by the hardware. Such clocks can be
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* considered by the software to be enabled. The current status
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* of auto-gated clocks can be read from the gate status bit.
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* - software-only gating
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* Auto-gating is not available for this type of clock.
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* Instead, software manages whether it's enabled by setting or
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* clearing the enable bit. The current gate status of a gate
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* under software control can be read from the gate status bit.
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* To ensure a change to the gating status is complete, the
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* status bit can be polled to verify that the gate has entered
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* the desired state.
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* - selectable hardware or software gating
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* Gating for this type of clock can be configured to be either
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* under software or hardware control. Which type is in use is
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* determined by the hw_sw_sel bit of the gate register.
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*/
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struct bcm_clk_gate {
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u32 offset; /* gate register offset */
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u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
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u32 en_bit; /* 0: disable; 1: enable */
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u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
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u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
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};
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/*
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* Gate flags:
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* HW means this gate can be auto-gated
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* SW means the state of this gate can be software controlled
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* NO_DISABLE means this gate is (only) enabled if under software control
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* SW_MANAGED means the status of this gate is under software control
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* ENABLED means this software-managed gate is *supposed* to be enabled
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*/
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#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
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#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
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#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
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#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
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#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
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#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
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/*
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* Gate initialization macros.
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*
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* Any gate initially under software control will be enabled.
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*/
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/* A hardware/software gate initially under software control */
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#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
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{ \
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.offset = (_offset), \
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.status_bit = (_status_bit), \
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.en_bit = (_en_bit), \
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.hw_sw_sel_bit = (_hw_sw_sel_bit), \
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.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
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FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
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FLAG(GATE, EXISTS), \
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}
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/* A hardware/software gate initially under hardware control */
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#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
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{ \
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.offset = (_offset), \
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.status_bit = (_status_bit), \
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.en_bit = (_en_bit), \
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.hw_sw_sel_bit = (_hw_sw_sel_bit), \
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.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
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FLAG(GATE, EXISTS), \
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}
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/* A hardware-or-enabled gate (enabled if not under hardware control) */
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#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
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{ \
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.offset = (_offset), \
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.status_bit = (_status_bit), \
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.en_bit = (_en_bit), \
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.hw_sw_sel_bit = (_hw_sw_sel_bit), \
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.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
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FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
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}
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/* A software-only gate */
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#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
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{ \
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.offset = (_offset), \
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.status_bit = (_status_bit), \
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.en_bit = (_en_bit), \
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.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
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FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
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}
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/* A hardware-only gate */
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#define HW_ONLY_GATE(_offset, _status_bit) \
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{ \
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.offset = (_offset), \
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.status_bit = (_status_bit), \
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.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
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}
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/* Gate hysteresis for clocks */
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struct bcm_clk_hyst {
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u32 offset; /* hyst register offset (normally CLKGATE) */
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u32 en_bit; /* bit used to enable hysteresis */
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u32 val_bit; /* if enabled: 0 = low delay; 1 = high delay */
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};
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/* Hysteresis initialization macro */
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#define HYST(_offset, _en_bit, _val_bit) \
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{ \
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.offset = (_offset), \
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.en_bit = (_en_bit), \
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.val_bit = (_val_bit), \
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}
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/*
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* Each clock can have zero, one, or two dividers which change the
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* output rate of the clock. Each divider can be either fixed or
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* variable. If there are two dividers, they are the "pre-divider"
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* and the "regular" or "downstream" divider. If there is only one,
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* there is no pre-divider.
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*
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* A fixed divider is any non-zero (positive) value, and it
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* indicates how the input rate is affected by the divider.
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*
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* The value of a variable divider is maintained in a sub-field of a
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* 32-bit divider register. The position of the field in the
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* register is defined by its offset and width. The value recorded
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* in this field is always 1 less than the value it represents.
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*
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* In addition, a variable divider can indicate that some subset
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* of its bits represent a "fractional" part of the divider. Such
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* bits comprise the low-order portion of the divider field, and can
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* be viewed as representing the portion of the divider that lies to
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* the right of the decimal point. Most variable dividers have zero
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* fractional bits. Variable dividers with non-zero fraction width
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* still record a value 1 less than the value they represent; the
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* added 1 does *not* affect the low-order bit in this case, it
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* affects the bits above the fractional part only. (Often in this
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* code a divider field value is distinguished from the value it
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* represents by referring to the latter as a "divisor".)
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*
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* In order to avoid dealing with fractions, divider arithmetic is
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* performed using "scaled" values. A scaled value is one that's
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* been left-shifted by the fractional width of a divider. Dividing
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* a scaled value by a scaled divisor produces the desired quotient
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* without loss of precision and without any other special handling
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* for fractions.
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*
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* The recorded value of a variable divider can be modified. To
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* modify either divider (or both), a clock must be enabled (i.e.,
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* using its gate). In addition, a trigger register (described
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* below) must be used to commit the change, and polled to verify
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* the change is complete.
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*/
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struct bcm_clk_div {
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union {
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struct { /* variable divider */
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u32 offset; /* divider register offset */
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u32 shift; /* field shift */
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u32 width; /* field width */
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u32 frac_width; /* field fraction width */
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u64 scaled_div; /* scaled divider value */
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} s;
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u32 fixed; /* non-zero fixed divider value */
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} u;
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u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
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};
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/*
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* Divider flags:
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* EXISTS means this divider exists
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* FIXED means it is a fixed-rate divider
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*/
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#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
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#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
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/* Divider initialization macros */
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/* A fixed (non-zero) divider */
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#define FIXED_DIVIDER(_value) \
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{ \
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.u.fixed = (_value), \
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.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
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}
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/* A divider with an integral divisor */
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#define DIVIDER(_offset, _shift, _width) \
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{ \
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.u.s.offset = (_offset), \
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.u.s.shift = (_shift), \
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.u.s.width = (_width), \
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.u.s.scaled_div = BAD_SCALED_DIV_VALUE, \
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.flags = FLAG(DIV, EXISTS), \
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}
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/* A divider whose divisor has an integer and fractional part */
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#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
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{ \
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.u.s.offset = (_offset), \
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.u.s.shift = (_shift), \
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.u.s.width = (_width), \
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.u.s.frac_width = (_frac_width), \
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.u.s.scaled_div = BAD_SCALED_DIV_VALUE, \
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.flags = FLAG(DIV, EXISTS), \
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}
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/*
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* Clocks may have multiple "parent" clocks. If there is more than
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* one, a selector must be specified to define which of the parent
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* clocks is currently in use. The selected clock is indicated in a
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* sub-field of a 32-bit selector register. The range of
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* representable selector values typically exceeds the number of
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* available parent clocks. Occasionally the reset value of a
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* selector field is explicitly set to a (specific) value that does
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* not correspond to a defined input clock.
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*
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* We register all known parent clocks with the common clock code
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* using a packed array (i.e., no empty slots) of (parent) clock
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* names, and refer to them later using indexes into that array.
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* We maintain an array of selector values indexed by common clock
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* index values in order to map between these common clock indexes
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* and the selector values used by the hardware.
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*
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* Like dividers, a selector can be modified, but to do so a clock
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* must be enabled, and a trigger must be used to commit the change.
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*/
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struct bcm_clk_sel {
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u32 offset; /* selector register offset */
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u32 shift; /* field shift */
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u32 width; /* field width */
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u32 parent_count; /* number of entries in parent_sel[] */
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u32 *parent_sel; /* array of parent selector values */
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u8 clk_index; /* current selected index in parent_sel[] */
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};
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/* Selector initialization macro */
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#define SELECTOR(_offset, _shift, _width) \
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{ \
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.offset = (_offset), \
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.shift = (_shift), \
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.width = (_width), \
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.clk_index = BAD_CLK_INDEX, \
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}
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/*
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* Making changes to a variable divider or a selector for a clock
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* requires the use of a trigger. A trigger is defined by a single
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* bit within a register. To signal a change, a 1 is written into
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* that bit. To determine when the change has been completed, that
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* trigger bit is polled; the read value will be 1 while the change
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* is in progress, and 0 when it is complete.
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*
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* Occasionally a clock will have more than one trigger. In this
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* case, the "pre-trigger" will be used when changing a clock's
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* selector and/or its pre-divider.
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*/
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struct bcm_clk_trig {
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u32 offset; /* trigger register offset */
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u32 bit; /* trigger bit */
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u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
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};
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/*
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* Trigger flags:
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* EXISTS means this trigger exists
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*/
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#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
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/* Trigger initialization macro */
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#define TRIGGER(_offset, _bit) \
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{ \
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.offset = (_offset), \
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.bit = (_bit), \
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.flags = FLAG(TRIG, EXISTS), \
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}
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struct peri_clk_data {
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struct bcm_clk_policy policy;
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struct bcm_clk_gate gate;
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struct bcm_clk_hyst hyst;
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struct bcm_clk_trig pre_trig;
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struct bcm_clk_div pre_div;
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struct bcm_clk_trig trig;
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struct bcm_clk_div div;
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struct bcm_clk_sel sel;
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const char *clocks[]; /* must be last; use CLOCKS() to declare */
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};
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#define CLOCKS(...) { __VA_ARGS__, NULL, }
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#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
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struct kona_clk {
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struct clk_hw hw;
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struct clk_init_data init_data; /* includes name of this clock */
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struct ccu_data *ccu; /* ccu this clock is associated with */
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enum bcm_clk_type type;
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union {
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void *data;
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struct peri_clk_data *peri;
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} u;
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};
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#define to_kona_clk(_hw) \
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container_of(_hw, struct kona_clk, hw)
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/* Initialization macro for an entry in a CCU's kona_clks[] array. */
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#define KONA_CLK(_ccu_name, _clk_name, _type) \
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{ \
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.init_data = { \
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.name = #_clk_name, \
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.ops = &kona_ ## _type ## _clk_ops, \
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}, \
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.ccu = &_ccu_name ## _ccu_data, \
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.type = bcm_clk_ ## _type, \
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.u.data = &_clk_name ## _data, \
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}
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#define LAST_KONA_CLK { .type = bcm_clk_none }
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/*
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* CCU policy control. To enable software update of the policy
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* tables the CCU policy engine must be stopped by setting the
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* software update enable bit (LVM_EN). After an update the engine
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* is restarted using the GO bit and either the GO_ATL or GO_AC bit.
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*/
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struct bcm_lvm_en {
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u32 offset; /* LVM_EN register offset */
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u32 bit; /* POLICY_CONFIG_EN bit in register */
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};
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/* Policy enable initialization macro */
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#define CCU_LVM_EN(_offset, _bit) \
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{ \
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.offset = (_offset), \
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.bit = (_bit), \
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}
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struct bcm_policy_ctl {
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u32 offset; /* POLICY_CTL register offset */
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u32 go_bit;
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u32 atl_bit; /* GO, GO_ATL, and GO_AC bits */
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u32 ac_bit;
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};
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/* Policy control initialization macro */
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#define CCU_POLICY_CTL(_offset, _go_bit, _ac_bit, _atl_bit) \
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{ \
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.offset = (_offset), \
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.go_bit = (_go_bit), \
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.ac_bit = (_ac_bit), \
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.atl_bit = (_atl_bit), \
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}
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struct ccu_policy {
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struct bcm_lvm_en enable;
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struct bcm_policy_ctl control;
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};
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/*
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* Each CCU defines a mapped area of memory containing registers
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* used to manage clocks implemented by the CCU. Access to memory
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* within the CCU's space is serialized by a spinlock. Before any
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* (other) address can be written, a special access "password" value
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* must be written to its WR_ACCESS register (located at the base
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* address of the range). We keep track of the name of each CCU as
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* it is set up, and maintain them in a list.
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*/
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struct ccu_data {
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void __iomem *base; /* base of mapped address space */
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spinlock_t lock; /* serialization lock */
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bool write_enabled; /* write access is currently enabled */
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struct ccu_policy policy;
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struct device_node *node;
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size_t clk_num;
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const char *name;
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u32 range; /* byte range of address space */
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struct kona_clk kona_clks[]; /* must be last */
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};
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/* Initialization for common fields in a Kona ccu_data structure */
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#define KONA_CCU_COMMON(_prefix, _name, _ccuname) \
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.name = #_name "_ccu", \
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.lock = __SPIN_LOCK_UNLOCKED(_name ## _ccu_data.lock), \
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.clk_num = _prefix ## _ ## _ccuname ## _CCU_CLOCK_COUNT
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/* Exported globals */
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extern struct clk_ops kona_peri_clk_ops;
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/* Externally visible functions */
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extern u64 scaled_div_max(struct bcm_clk_div *div);
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extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value,
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u32 billionths);
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extern void __init kona_dt_ccu_setup(struct ccu_data *ccu,
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struct device_node *node);
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extern bool __init kona_ccu_init(struct ccu_data *ccu);
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#endif /* _CLK_KONA_H */
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