753 lines
24 KiB
ArmAsm
753 lines
24 KiB
ArmAsm
########################################################################
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# Implement fast SHA-512 with AVX2 instructions. (x86_64)
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#
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# Copyright (C) 2013 Intel Corporation.
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#
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# Authors:
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# James Guilford <james.guilford@intel.com>
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# Kirk Yap <kirk.s.yap@intel.com>
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# David Cote <david.m.cote@intel.com>
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# Tim Chen <tim.c.chen@linux.intel.com>
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#
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# This software is available to you under a choice of one of two
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# licenses. You may choose to be licensed under the terms of the GNU
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# General Public License (GPL) Version 2, available from the file
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# COPYING in the main directory of this source tree, or the
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# OpenIB.org BSD license below:
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#
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# Redistribution and use in source and binary forms, with or
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# without modification, are permitted provided that the following
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# conditions are met:
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#
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# - Redistributions of source code must retain the above
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# copyright notice, this list of conditions and the following
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# disclaimer.
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#
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# - Redistributions in binary form must reproduce the above
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# copyright notice, this list of conditions and the following
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# disclaimer in the documentation and/or other materials
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# provided with the distribution.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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########################################################################
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#
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# This code is described in an Intel White-Paper:
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# "Fast SHA-512 Implementations on Intel Architecture Processors"
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#
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# To find it, surf to http://www.intel.com/p/en_US/embedded
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# and search for that title.
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#
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########################################################################
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# This code schedules 1 blocks at a time, with 4 lanes per block
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########################################################################
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#ifdef CONFIG_AS_AVX2
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#include <linux/linkage.h>
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.text
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# Virtual Registers
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Y_0 = %ymm4
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Y_1 = %ymm5
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Y_2 = %ymm6
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Y_3 = %ymm7
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YTMP0 = %ymm0
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YTMP1 = %ymm1
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YTMP2 = %ymm2
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YTMP3 = %ymm3
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YTMP4 = %ymm8
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XFER = YTMP0
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BYTE_FLIP_MASK = %ymm9
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# 1st arg is %rdi, which is saved to the stack and accessed later via %r12
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CTX1 = %rdi
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CTX2 = %r12
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# 2nd arg
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INP = %rsi
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# 3rd arg
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NUM_BLKS = %rdx
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c = %rcx
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d = %r8
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e = %rdx
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y3 = %rsi
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TBL = %rdi # clobbers CTX1
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a = %rax
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b = %rbx
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f = %r9
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g = %r10
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h = %r11
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old_h = %r11
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T1 = %r12 # clobbers CTX2
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y0 = %r13
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y1 = %r14
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y2 = %r15
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# Local variables (stack frame)
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XFER_SIZE = 4*8
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SRND_SIZE = 1*8
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INP_SIZE = 1*8
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INPEND_SIZE = 1*8
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CTX_SIZE = 1*8
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RSPSAVE_SIZE = 1*8
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GPRSAVE_SIZE = 5*8
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frame_XFER = 0
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frame_SRND = frame_XFER + XFER_SIZE
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frame_INP = frame_SRND + SRND_SIZE
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frame_INPEND = frame_INP + INP_SIZE
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frame_CTX = frame_INPEND + INPEND_SIZE
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frame_RSPSAVE = frame_CTX + CTX_SIZE
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frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
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frame_size = frame_GPRSAVE + GPRSAVE_SIZE
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## assume buffers not aligned
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#define VMOVDQ vmovdqu
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# addm [mem], reg
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# Add reg to mem using reg-mem add and store
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.macro addm p1 p2
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add \p1, \p2
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mov \p2, \p1
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.endm
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# COPY_YMM_AND_BSWAP ymm, [mem], byte_flip_mask
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# Load ymm with mem and byte swap each dword
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.macro COPY_YMM_AND_BSWAP p1 p2 p3
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VMOVDQ \p2, \p1
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vpshufb \p3, \p1, \p1
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.endm
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# rotate_Ys
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# Rotate values of symbols Y0...Y3
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.macro rotate_Ys
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Y_ = Y_0
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Y_0 = Y_1
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Y_1 = Y_2
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Y_2 = Y_3
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Y_3 = Y_
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.endm
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# RotateState
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.macro RotateState
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# Rotate symbols a..h right
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old_h = h
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TMP_ = h
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h = g
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g = f
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f = e
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e = d
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d = c
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c = b
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b = a
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a = TMP_
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.endm
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# macro MY_VPALIGNR YDST, YSRC1, YSRC2, RVAL
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# YDST = {YSRC1, YSRC2} >> RVAL*8
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.macro MY_VPALIGNR YDST YSRC1 YSRC2 RVAL
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vperm2f128 $0x3, \YSRC2, \YSRC1, \YDST # YDST = {YS1_LO, YS2_HI}
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vpalignr $\RVAL, \YSRC2, \YDST, \YDST # YDST = {YDS1, YS2} >> RVAL*8
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.endm
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.macro FOUR_ROUNDS_AND_SCHED
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################################### RND N + 0 #########################################
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# Extract w[t-7]
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MY_VPALIGNR YTMP0, Y_3, Y_2, 8 # YTMP0 = W[-7]
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# Calculate w[t-16] + w[t-7]
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vpaddq Y_0, YTMP0, YTMP0 # YTMP0 = W[-7] + W[-16]
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# Extract w[t-15]
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MY_VPALIGNR YTMP1, Y_1, Y_0, 8 # YTMP1 = W[-15]
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# Calculate sigma0
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# Calculate w[t-15] ror 1
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vpsrlq $1, YTMP1, YTMP2
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vpsllq $(64-1), YTMP1, YTMP3
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vpor YTMP2, YTMP3, YTMP3 # YTMP3 = W[-15] ror 1
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# Calculate w[t-15] shr 7
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vpsrlq $7, YTMP1, YTMP4 # YTMP4 = W[-15] >> 7
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mov a, y3 # y3 = a # MAJA
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rorx $41, e, y0 # y0 = e >> 41 # S1A
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rorx $18, e, y1 # y1 = e >> 18 # S1B
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add frame_XFER(%rsp),h # h = k + w + h # --
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or c, y3 # y3 = a|c # MAJA
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mov f, y2 # y2 = f # CH
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rorx $34, a, T1 # T1 = a >> 34 # S0B
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
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xor g, y2 # y2 = f^g # CH
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rorx $14, e, y1 # y1 = (e >> 14) # S1
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and e, y2 # y2 = (f^g)&e # CH
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
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rorx $39, a, y1 # y1 = a >> 39 # S0A
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add h, d # d = k + w + h + d # --
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and b, y3 # y3 = (a|c)&b # MAJA
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
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rorx $28, a, T1 # T1 = (a >> 28) # S0
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xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
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mov a, T1 # T1 = a # MAJB
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and c, T1 # T1 = a&c # MAJB
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add y0, y2 # y2 = S1 + CH # --
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or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
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add y1, h # h = k + w + h + S0 # --
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add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
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add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
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add y3, h # h = t1 + S0 + MAJ # --
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RotateState
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################################### RND N + 1 #########################################
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# Calculate w[t-15] ror 8
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vpsrlq $8, YTMP1, YTMP2
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vpsllq $(64-8), YTMP1, YTMP1
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vpor YTMP2, YTMP1, YTMP1 # YTMP1 = W[-15] ror 8
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# XOR the three components
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vpxor YTMP4, YTMP3, YTMP3 # YTMP3 = W[-15] ror 1 ^ W[-15] >> 7
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vpxor YTMP1, YTMP3, YTMP1 # YTMP1 = s0
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# Add three components, w[t-16], w[t-7] and sigma0
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vpaddq YTMP1, YTMP0, YTMP0 # YTMP0 = W[-16] + W[-7] + s0
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# Move to appropriate lanes for calculating w[16] and w[17]
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vperm2f128 $0x0, YTMP0, YTMP0, Y_0 # Y_0 = W[-16] + W[-7] + s0 {BABA}
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# Move to appropriate lanes for calculating w[18] and w[19]
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vpand MASK_YMM_LO(%rip), YTMP0, YTMP0 # YTMP0 = W[-16] + W[-7] + s0 {DC00}
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# Calculate w[16] and w[17] in both 128 bit lanes
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# Calculate sigma1 for w[16] and w[17] on both 128 bit lanes
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vperm2f128 $0x11, Y_3, Y_3, YTMP2 # YTMP2 = W[-2] {BABA}
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vpsrlq $6, YTMP2, YTMP4 # YTMP4 = W[-2] >> 6 {BABA}
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mov a, y3 # y3 = a # MAJA
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rorx $41, e, y0 # y0 = e >> 41 # S1A
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rorx $18, e, y1 # y1 = e >> 18 # S1B
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add 1*8+frame_XFER(%rsp), h # h = k + w + h # --
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or c, y3 # y3 = a|c # MAJA
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mov f, y2 # y2 = f # CH
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rorx $34, a, T1 # T1 = a >> 34 # S0B
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
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xor g, y2 # y2 = f^g # CH
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rorx $14, e, y1 # y1 = (e >> 14) # S1
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
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rorx $39, a, y1 # y1 = a >> 39 # S0A
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and e, y2 # y2 = (f^g)&e # CH
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add h, d # d = k + w + h + d # --
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and b, y3 # y3 = (a|c)&b # MAJA
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
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rorx $28, a, T1 # T1 = (a >> 28) # S0
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xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
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mov a, T1 # T1 = a # MAJB
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and c, T1 # T1 = a&c # MAJB
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add y0, y2 # y2 = S1 + CH # --
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or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
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add y1, h # h = k + w + h + S0 # --
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add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
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add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
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add y3, h # h = t1 + S0 + MAJ # --
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RotateState
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################################### RND N + 2 #########################################
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vpsrlq $19, YTMP2, YTMP3 # YTMP3 = W[-2] >> 19 {BABA}
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vpsllq $(64-19), YTMP2, YTMP1 # YTMP1 = W[-2] << 19 {BABA}
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vpor YTMP1, YTMP3, YTMP3 # YTMP3 = W[-2] ror 19 {BABA}
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vpxor YTMP3, YTMP4, YTMP4 # YTMP4 = W[-2] ror 19 ^ W[-2] >> 6 {BABA}
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vpsrlq $61, YTMP2, YTMP3 # YTMP3 = W[-2] >> 61 {BABA}
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vpsllq $(64-61), YTMP2, YTMP1 # YTMP1 = W[-2] << 61 {BABA}
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vpor YTMP1, YTMP3, YTMP3 # YTMP3 = W[-2] ror 61 {BABA}
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vpxor YTMP3, YTMP4, YTMP4 # YTMP4 = s1 = (W[-2] ror 19) ^
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# (W[-2] ror 61) ^ (W[-2] >> 6) {BABA}
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# Add sigma1 to the other compunents to get w[16] and w[17]
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vpaddq YTMP4, Y_0, Y_0 # Y_0 = {W[1], W[0], W[1], W[0]}
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# Calculate sigma1 for w[18] and w[19] for upper 128 bit lane
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vpsrlq $6, Y_0, YTMP4 # YTMP4 = W[-2] >> 6 {DC--}
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mov a, y3 # y3 = a # MAJA
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rorx $41, e, y0 # y0 = e >> 41 # S1A
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add 2*8+frame_XFER(%rsp), h # h = k + w + h # --
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rorx $18, e, y1 # y1 = e >> 18 # S1B
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or c, y3 # y3 = a|c # MAJA
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mov f, y2 # y2 = f # CH
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xor g, y2 # y2 = f^g # CH
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rorx $34, a, T1 # T1 = a >> 34 # S0B
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
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and e, y2 # y2 = (f^g)&e # CH
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rorx $14, e, y1 # y1 = (e >> 14) # S1
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add h, d # d = k + w + h + d # --
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and b, y3 # y3 = (a|c)&b # MAJA
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
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rorx $39, a, y1 # y1 = a >> 39 # S0A
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xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
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rorx $28, a, T1 # T1 = (a >> 28) # S0
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
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mov a, T1 # T1 = a # MAJB
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and c, T1 # T1 = a&c # MAJB
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add y0, y2 # y2 = S1 + CH # --
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or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
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add y1, h # h = k + w + h + S0 # --
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add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
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add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
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add y3, h # h = t1 + S0 + MAJ # --
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RotateState
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################################### RND N + 3 #########################################
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vpsrlq $19, Y_0, YTMP3 # YTMP3 = W[-2] >> 19 {DC--}
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vpsllq $(64-19), Y_0, YTMP1 # YTMP1 = W[-2] << 19 {DC--}
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vpor YTMP1, YTMP3, YTMP3 # YTMP3 = W[-2] ror 19 {DC--}
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vpxor YTMP3, YTMP4, YTMP4 # YTMP4 = W[-2] ror 19 ^ W[-2] >> 6 {DC--}
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vpsrlq $61, Y_0, YTMP3 # YTMP3 = W[-2] >> 61 {DC--}
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vpsllq $(64-61), Y_0, YTMP1 # YTMP1 = W[-2] << 61 {DC--}
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vpor YTMP1, YTMP3, YTMP3 # YTMP3 = W[-2] ror 61 {DC--}
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vpxor YTMP3, YTMP4, YTMP4 # YTMP4 = s1 = (W[-2] ror 19) ^
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# (W[-2] ror 61) ^ (W[-2] >> 6) {DC--}
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# Add the sigma0 + w[t-7] + w[t-16] for w[18] and w[19]
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# to newly calculated sigma1 to get w[18] and w[19]
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vpaddq YTMP4, YTMP0, YTMP2 # YTMP2 = {W[3], W[2], --, --}
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# Form w[19, w[18], w17], w[16]
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vpblendd $0xF0, YTMP2, Y_0, Y_0 # Y_0 = {W[3], W[2], W[1], W[0]}
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mov a, y3 # y3 = a # MAJA
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rorx $41, e, y0 # y0 = e >> 41 # S1A
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rorx $18, e, y1 # y1 = e >> 18 # S1B
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add 3*8+frame_XFER(%rsp), h # h = k + w + h # --
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or c, y3 # y3 = a|c # MAJA
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mov f, y2 # y2 = f # CH
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rorx $34, a, T1 # T1 = a >> 34 # S0B
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
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xor g, y2 # y2 = f^g # CH
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rorx $14, e, y1 # y1 = (e >> 14) # S1
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and e, y2 # y2 = (f^g)&e # CH
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add h, d # d = k + w + h + d # --
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and b, y3 # y3 = (a|c)&b # MAJA
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xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
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xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
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rorx $39, a, y1 # y1 = a >> 39 # S0A
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add y0, y2 # y2 = S1 + CH # --
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
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add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
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rorx $28, a, T1 # T1 = (a >> 28) # S0
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xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
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mov a, T1 # T1 = a # MAJB
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and c, T1 # T1 = a&c # MAJB
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or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
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add y1, h # h = k + w + h + S0 # --
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add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
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add y3, h # h = t1 + S0 + MAJ # --
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RotateState
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rotate_Ys
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.endm
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.macro DO_4ROUNDS
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################################### RND N + 0 #########################################
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|
|
|
mov f, y2 # y2 = f # CH
|
|
rorx $41, e, y0 # y0 = e >> 41 # S1A
|
|
rorx $18, e, y1 # y1 = e >> 18 # S1B
|
|
xor g, y2 # y2 = f^g # CH
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
|
|
rorx $14, e, y1 # y1 = (e >> 14) # S1
|
|
and e, y2 # y2 = (f^g)&e # CH
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
|
|
rorx $34, a, T1 # T1 = a >> 34 # S0B
|
|
xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
|
|
rorx $39, a, y1 # y1 = a >> 39 # S0A
|
|
mov a, y3 # y3 = a # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
|
|
rorx $28, a, T1 # T1 = (a >> 28) # S0
|
|
add frame_XFER(%rsp), h # h = k + w + h # --
|
|
or c, y3 # y3 = a|c # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
|
|
mov a, T1 # T1 = a # MAJB
|
|
and b, y3 # y3 = (a|c)&b # MAJA
|
|
and c, T1 # T1 = a&c # MAJB
|
|
add y0, y2 # y2 = S1 + CH # --
|
|
|
|
add h, d # d = k + w + h + d # --
|
|
or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
|
|
add y1, h # h = k + w + h + S0 # --
|
|
|
|
add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
|
|
|
|
RotateState
|
|
|
|
################################### RND N + 1 #########################################
|
|
|
|
add y2, old_h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
|
|
mov f, y2 # y2 = f # CH
|
|
rorx $41, e, y0 # y0 = e >> 41 # S1A
|
|
rorx $18, e, y1 # y1 = e >> 18 # S1B
|
|
xor g, y2 # y2 = f^g # CH
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
|
|
rorx $14, e, y1 # y1 = (e >> 14) # S1
|
|
and e, y2 # y2 = (f^g)&e # CH
|
|
add y3, old_h # h = t1 + S0 + MAJ # --
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
|
|
rorx $34, a, T1 # T1 = a >> 34 # S0B
|
|
xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
|
|
rorx $39, a, y1 # y1 = a >> 39 # S0A
|
|
mov a, y3 # y3 = a # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
|
|
rorx $28, a, T1 # T1 = (a >> 28) # S0
|
|
add 8*1+frame_XFER(%rsp), h # h = k + w + h # --
|
|
or c, y3 # y3 = a|c # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
|
|
mov a, T1 # T1 = a # MAJB
|
|
and b, y3 # y3 = (a|c)&b # MAJA
|
|
and c, T1 # T1 = a&c # MAJB
|
|
add y0, y2 # y2 = S1 + CH # --
|
|
|
|
add h, d # d = k + w + h + d # --
|
|
or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
|
|
add y1, h # h = k + w + h + S0 # --
|
|
|
|
add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
|
|
|
|
RotateState
|
|
|
|
################################### RND N + 2 #########################################
|
|
|
|
add y2, old_h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
|
|
mov f, y2 # y2 = f # CH
|
|
rorx $41, e, y0 # y0 = e >> 41 # S1A
|
|
rorx $18, e, y1 # y1 = e >> 18 # S1B
|
|
xor g, y2 # y2 = f^g # CH
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
|
|
rorx $14, e, y1 # y1 = (e >> 14) # S1
|
|
and e, y2 # y2 = (f^g)&e # CH
|
|
add y3, old_h # h = t1 + S0 + MAJ # --
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
|
|
rorx $34, a, T1 # T1 = a >> 34 # S0B
|
|
xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
|
|
rorx $39, a, y1 # y1 = a >> 39 # S0A
|
|
mov a, y3 # y3 = a # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
|
|
rorx $28, a, T1 # T1 = (a >> 28) # S0
|
|
add 8*2+frame_XFER(%rsp), h # h = k + w + h # --
|
|
or c, y3 # y3 = a|c # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
|
|
mov a, T1 # T1 = a # MAJB
|
|
and b, y3 # y3 = (a|c)&b # MAJA
|
|
and c, T1 # T1 = a&c # MAJB
|
|
add y0, y2 # y2 = S1 + CH # --
|
|
|
|
add h, d # d = k + w + h + d # --
|
|
or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
|
|
add y1, h # h = k + w + h + S0 # --
|
|
|
|
add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
|
|
|
|
RotateState
|
|
|
|
################################### RND N + 3 #########################################
|
|
|
|
add y2, old_h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
|
|
mov f, y2 # y2 = f # CH
|
|
rorx $41, e, y0 # y0 = e >> 41 # S1A
|
|
rorx $18, e, y1 # y1 = e >> 18 # S1B
|
|
xor g, y2 # y2 = f^g # CH
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) # S1
|
|
rorx $14, e, y1 # y1 = (e >> 14) # S1
|
|
and e, y2 # y2 = (f^g)&e # CH
|
|
add y3, old_h # h = t1 + S0 + MAJ # --
|
|
|
|
xor y1, y0 # y0 = (e>>41) ^ (e>>18) ^ (e>>14) # S1
|
|
rorx $34, a, T1 # T1 = a >> 34 # S0B
|
|
xor g, y2 # y2 = CH = ((f^g)&e)^g # CH
|
|
rorx $39, a, y1 # y1 = a >> 39 # S0A
|
|
mov a, y3 # y3 = a # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) # S0
|
|
rorx $28, a, T1 # T1 = (a >> 28) # S0
|
|
add 8*3+frame_XFER(%rsp), h # h = k + w + h # --
|
|
or c, y3 # y3 = a|c # MAJA
|
|
|
|
xor T1, y1 # y1 = (a>>39) ^ (a>>34) ^ (a>>28) # S0
|
|
mov a, T1 # T1 = a # MAJB
|
|
and b, y3 # y3 = (a|c)&b # MAJA
|
|
and c, T1 # T1 = a&c # MAJB
|
|
add y0, y2 # y2 = S1 + CH # --
|
|
|
|
|
|
add h, d # d = k + w + h + d # --
|
|
or T1, y3 # y3 = MAJ = (a|c)&b)|(a&c) # MAJ
|
|
add y1, h # h = k + w + h + S0 # --
|
|
|
|
add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
|
|
|
|
add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
|
|
|
|
add y3, h # h = t1 + S0 + MAJ # --
|
|
|
|
RotateState
|
|
|
|
.endm
|
|
|
|
########################################################################
|
|
# void sha512_transform_rorx(void* D, const void* M, uint64_t L)#
|
|
# Purpose: Updates the SHA512 digest stored at D with the message stored in M.
|
|
# The size of the message pointed to by M must be an integer multiple of SHA512
|
|
# message blocks.
|
|
# L is the message length in SHA512 blocks
|
|
########################################################################
|
|
ENTRY(sha512_transform_rorx)
|
|
# Allocate Stack Space
|
|
mov %rsp, %rax
|
|
sub $frame_size, %rsp
|
|
and $~(0x20 - 1), %rsp
|
|
mov %rax, frame_RSPSAVE(%rsp)
|
|
|
|
# Save GPRs
|
|
mov %rbx, 8*0+frame_GPRSAVE(%rsp)
|
|
mov %r12, 8*1+frame_GPRSAVE(%rsp)
|
|
mov %r13, 8*2+frame_GPRSAVE(%rsp)
|
|
mov %r14, 8*3+frame_GPRSAVE(%rsp)
|
|
mov %r15, 8*4+frame_GPRSAVE(%rsp)
|
|
|
|
shl $7, NUM_BLKS # convert to bytes
|
|
jz done_hash
|
|
add INP, NUM_BLKS # pointer to end of data
|
|
mov NUM_BLKS, frame_INPEND(%rsp)
|
|
|
|
## load initial digest
|
|
mov 8*0(CTX1), a
|
|
mov 8*1(CTX1), b
|
|
mov 8*2(CTX1), c
|
|
mov 8*3(CTX1), d
|
|
mov 8*4(CTX1), e
|
|
mov 8*5(CTX1), f
|
|
mov 8*6(CTX1), g
|
|
mov 8*7(CTX1), h
|
|
|
|
# save %rdi (CTX) before it gets clobbered
|
|
mov %rdi, frame_CTX(%rsp)
|
|
|
|
vmovdqa PSHUFFLE_BYTE_FLIP_MASK(%rip), BYTE_FLIP_MASK
|
|
|
|
loop0:
|
|
lea K512(%rip), TBL
|
|
|
|
## byte swap first 16 dwords
|
|
COPY_YMM_AND_BSWAP Y_0, (INP), BYTE_FLIP_MASK
|
|
COPY_YMM_AND_BSWAP Y_1, 1*32(INP), BYTE_FLIP_MASK
|
|
COPY_YMM_AND_BSWAP Y_2, 2*32(INP), BYTE_FLIP_MASK
|
|
COPY_YMM_AND_BSWAP Y_3, 3*32(INP), BYTE_FLIP_MASK
|
|
|
|
mov INP, frame_INP(%rsp)
|
|
|
|
## schedule 64 input dwords, by doing 12 rounds of 4 each
|
|
movq $4, frame_SRND(%rsp)
|
|
|
|
.align 16
|
|
loop1:
|
|
vpaddq (TBL), Y_0, XFER
|
|
vmovdqa XFER, frame_XFER(%rsp)
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
vpaddq 1*32(TBL), Y_0, XFER
|
|
vmovdqa XFER, frame_XFER(%rsp)
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
vpaddq 2*32(TBL), Y_0, XFER
|
|
vmovdqa XFER, frame_XFER(%rsp)
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
vpaddq 3*32(TBL), Y_0, XFER
|
|
vmovdqa XFER, frame_XFER(%rsp)
|
|
add $(4*32), TBL
|
|
FOUR_ROUNDS_AND_SCHED
|
|
|
|
subq $1, frame_SRND(%rsp)
|
|
jne loop1
|
|
|
|
movq $2, frame_SRND(%rsp)
|
|
loop2:
|
|
vpaddq (TBL), Y_0, XFER
|
|
vmovdqa XFER, frame_XFER(%rsp)
|
|
DO_4ROUNDS
|
|
vpaddq 1*32(TBL), Y_1, XFER
|
|
vmovdqa XFER, frame_XFER(%rsp)
|
|
add $(2*32), TBL
|
|
DO_4ROUNDS
|
|
|
|
vmovdqa Y_2, Y_0
|
|
vmovdqa Y_3, Y_1
|
|
|
|
subq $1, frame_SRND(%rsp)
|
|
jne loop2
|
|
|
|
mov frame_CTX(%rsp), CTX2
|
|
addm 8*0(CTX2), a
|
|
addm 8*1(CTX2), b
|
|
addm 8*2(CTX2), c
|
|
addm 8*3(CTX2), d
|
|
addm 8*4(CTX2), e
|
|
addm 8*5(CTX2), f
|
|
addm 8*6(CTX2), g
|
|
addm 8*7(CTX2), h
|
|
|
|
mov frame_INP(%rsp), INP
|
|
add $128, INP
|
|
cmp frame_INPEND(%rsp), INP
|
|
jne loop0
|
|
|
|
done_hash:
|
|
|
|
# Restore GPRs
|
|
mov 8*0+frame_GPRSAVE(%rsp), %rbx
|
|
mov 8*1+frame_GPRSAVE(%rsp), %r12
|
|
mov 8*2+frame_GPRSAVE(%rsp), %r13
|
|
mov 8*3+frame_GPRSAVE(%rsp), %r14
|
|
mov 8*4+frame_GPRSAVE(%rsp), %r15
|
|
|
|
# Restore Stack Pointer
|
|
mov frame_RSPSAVE(%rsp), %rsp
|
|
ret
|
|
ENDPROC(sha512_transform_rorx)
|
|
|
|
########################################################################
|
|
### Binary Data
|
|
|
|
|
|
# Mergeable 640-byte rodata section. This allows linker to merge the table
|
|
# with other, exactly the same 640-byte fragment of another rodata section
|
|
# (if such section exists).
|
|
.section .rodata.cst640.K512, "aM", @progbits, 640
|
|
.align 64
|
|
# K[t] used in SHA512 hashing
|
|
K512:
|
|
.quad 0x428a2f98d728ae22,0x7137449123ef65cd
|
|
.quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
|
|
.quad 0x3956c25bf348b538,0x59f111f1b605d019
|
|
.quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
|
|
.quad 0xd807aa98a3030242,0x12835b0145706fbe
|
|
.quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
|
|
.quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
|
|
.quad 0x9bdc06a725c71235,0xc19bf174cf692694
|
|
.quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
|
|
.quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
|
|
.quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
|
|
.quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
|
|
.quad 0x983e5152ee66dfab,0xa831c66d2db43210
|
|
.quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
|
|
.quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
|
|
.quad 0x06ca6351e003826f,0x142929670a0e6e70
|
|
.quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
|
|
.quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
|
|
.quad 0x650a73548baf63de,0x766a0abb3c77b2a8
|
|
.quad 0x81c2c92e47edaee6,0x92722c851482353b
|
|
.quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
|
|
.quad 0xc24b8b70d0f89791,0xc76c51a30654be30
|
|
.quad 0xd192e819d6ef5218,0xd69906245565a910
|
|
.quad 0xf40e35855771202a,0x106aa07032bbd1b8
|
|
.quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
|
|
.quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
|
|
.quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
|
|
.quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
|
|
.quad 0x748f82ee5defb2fc,0x78a5636f43172f60
|
|
.quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
|
|
.quad 0x90befffa23631e28,0xa4506cebde82bde9
|
|
.quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
|
|
.quad 0xca273eceea26619c,0xd186b8c721c0c207
|
|
.quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
|
|
.quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
|
|
.quad 0x113f9804bef90dae,0x1b710b35131c471b
|
|
.quad 0x28db77f523047d84,0x32caab7b40c72493
|
|
.quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
|
|
.quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
|
|
.quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
|
|
|
|
.section .rodata.cst32.PSHUFFLE_BYTE_FLIP_MASK, "aM", @progbits, 32
|
|
.align 32
|
|
# Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
|
|
PSHUFFLE_BYTE_FLIP_MASK:
|
|
.octa 0x08090a0b0c0d0e0f0001020304050607
|
|
.octa 0x18191a1b1c1d1e1f1011121314151617
|
|
|
|
.section .rodata.cst32.MASK_YMM_LO, "aM", @progbits, 32
|
|
.align 32
|
|
MASK_YMM_LO:
|
|
.octa 0x00000000000000000000000000000000
|
|
.octa 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
|
|
|
|
#endif
|