144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/sh/boards/se/7724/irq.c
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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*
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on linux/arch/sh/boards/se/7722/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* Hitachi UL SolutionEngine 7724 Support.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/export.h>
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#include <linux/topology.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <mach-se/mach/se7724.h>
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struct fpga_irq {
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unsigned long sraddr;
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unsigned long mraddr;
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unsigned short mask;
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unsigned int base;
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};
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static unsigned int fpga2irq(unsigned int irq)
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{
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if (irq >= IRQ0_BASE &&
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irq <= IRQ0_END)
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return IRQ0_IRQ;
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else if (irq >= IRQ1_BASE &&
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irq <= IRQ1_END)
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return IRQ1_IRQ;
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else
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return IRQ2_IRQ;
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}
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static struct fpga_irq get_fpga_irq(unsigned int irq)
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{
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struct fpga_irq set;
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switch (irq) {
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case IRQ0_IRQ:
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set.sraddr = IRQ0_SR;
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set.mraddr = IRQ0_MR;
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set.mask = IRQ0_MASK;
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set.base = IRQ0_BASE;
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break;
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case IRQ1_IRQ:
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set.sraddr = IRQ1_SR;
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set.mraddr = IRQ1_MR;
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set.mask = IRQ1_MASK;
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set.base = IRQ1_BASE;
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break;
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default:
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set.sraddr = IRQ2_SR;
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set.mraddr = IRQ2_MR;
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set.mask = IRQ2_MASK;
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set.base = IRQ2_BASE;
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break;
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}
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return set;
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}
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static void disable_se7724_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
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unsigned int bit = irq - set.base;
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__raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
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}
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static void enable_se7724_irq(struct irq_data *data)
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{
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unsigned int irq = data->irq;
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struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
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unsigned int bit = irq - set.base;
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__raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
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}
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static struct irq_chip se7724_irq_chip __read_mostly = {
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.name = "SE7724-FPGA",
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.irq_mask = disable_se7724_irq,
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.irq_unmask = enable_se7724_irq,
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};
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static void se7724_irq_demux(struct irq_desc *desc)
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{
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unsigned int irq = irq_desc_get_irq(desc);
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struct fpga_irq set = get_fpga_irq(irq);
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unsigned short intv = __raw_readw(set.sraddr);
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unsigned int ext_irq = set.base;
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intv &= set.mask;
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for (; intv; intv >>= 1, ext_irq++) {
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if (!(intv & 1))
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continue;
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generic_handle_irq(ext_irq);
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}
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}
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7724_IRQ(void)
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{
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int irq_base, i;
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__raw_writew(0xffff, IRQ0_MR); /* mask all */
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__raw_writew(0xffff, IRQ1_MR); /* mask all */
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__raw_writew(0xffff, IRQ2_MR); /* mask all */
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__raw_writew(0x0000, IRQ0_SR); /* clear irq */
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__raw_writew(0x0000, IRQ1_SR); /* clear irq */
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__raw_writew(0x0000, IRQ2_SR); /* clear irq */
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__raw_writew(0x002a, IRQ_MODE); /* set irq type */
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irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE,
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SE7724_FPGA_IRQ_NR, numa_node_id());
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if (IS_ERR_VALUE(irq_base)) {
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pr_err("%s: failed hooking irqs for FPGA\n", __func__);
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return;
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}
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for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
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irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip,
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handle_level_irq, "level");
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irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux);
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irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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