441 lines
8.9 KiB
C
441 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Clock and PLL control for C64x+ devices
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*
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* Copyright (C) 2010, 2011 Texas Instruments.
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* Contributed by: Mark Salter <msalter@redhat.com>
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*
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* Copied heavily from arm/mach-davinci/clock.c, so:
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*
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* Copyright (C) 2006-2007 Texas Instruments.
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* Copyright (C) 2008-2009 Deep Root Systems, LLC
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*/
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#include <linux/module.h>
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <asm/clock.h>
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#include <asm/soc.h>
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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static DEFINE_SPINLOCK(clockfw_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (clk->parent)
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__clk_enable(clk->parent);
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clk->usecount++;
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}
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static void __clk_disable(struct clk *clk)
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{
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if (WARN_ON(clk->usecount == 0))
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return;
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--clk->usecount;
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return;
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spin_lock_irqsave(&clockfw_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (clk->round_rate)
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return clk->round_rate(clk, rate);
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_round_rate);
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/* Propagate rate to children */
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static void propagate_rate(struct clk *root)
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{
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struct clk *clk;
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list_for_each_entry(clk, &root->children, childnode) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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}
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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int ret = -EINVAL;
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if (clk == NULL || IS_ERR(clk))
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return ret;
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if (clk->set_rate)
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ret = clk->set_rate(clk, rate);
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spin_lock_irqsave(&clockfw_lock, flags);
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if (ret == 0) {
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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}
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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/* Cannot change parent on enabled clock */
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if (WARN_ON(clk->usecount))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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clk->parent = parent;
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list_del_init(&clk->childnode);
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list_add(&clk->childnode, &clk->parent->children);
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mutex_unlock(&clocks_mutex);
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spin_lock_irqsave(&clockfw_lock, flags);
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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propagate_rate(clk);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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int clk_register(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (WARN(clk->parent && !clk->parent->rate,
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"CLK: %s parent %s has no rate!\n",
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clk->name, clk->parent->name))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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list_add_tail(&clk->node, &clocks);
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if (clk->parent)
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list_add_tail(&clk->childnode, &clk->parent->children);
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mutex_unlock(&clocks_mutex);
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/* If rate is already set, use it */
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if (clk->rate)
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return 0;
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/* Else, see if there is a way to calculate it */
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if (clk->recalc)
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clk->rate = clk->recalc(clk);
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/* Otherwise, default to parent rate */
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else if (clk->parent)
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clk->rate = clk->parent->rate;
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return 0;
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}
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EXPORT_SYMBOL(clk_register);
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void clk_unregister(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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mutex_lock(&clocks_mutex);
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list_del(&clk->node);
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list_del(&clk->childnode);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_unregister);
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static u32 pll_read(struct pll_data *pll, int reg)
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{
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return soc_readl(pll->base + reg);
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}
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static unsigned long clk_sysclk_recalc(struct clk *clk)
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{
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u32 v, plldiv = 0;
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struct pll_data *pll;
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unsigned long rate = clk->rate;
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if (WARN_ON(!clk->parent))
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return rate;
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rate = clk->parent->rate;
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/* the parent must be a PLL */
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if (WARN_ON(!clk->parent->pll_data))
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return rate;
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pll = clk->parent->pll_data;
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/* If pre-PLL, source clock is before the multiplier and divider(s) */
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if (clk->flags & PRE_PLL)
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rate = pll->input_rate;
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if (!clk->div) {
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pr_debug("%s: (no divider) rate = %lu KHz\n",
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clk->name, rate / 1000);
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return rate;
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}
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if (clk->flags & FIXED_DIV_PLL) {
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rate /= clk->div;
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pr_debug("%s: (fixed divide by %d) rate = %lu KHz\n",
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clk->name, clk->div, rate / 1000);
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return rate;
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}
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v = pll_read(pll, clk->div);
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if (v & PLLDIV_EN)
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plldiv = (v & PLLDIV_RATIO_MASK) + 1;
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if (plldiv == 0)
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plldiv = 1;
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rate /= plldiv;
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pr_debug("%s: (divide by %d) rate = %lu KHz\n",
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clk->name, plldiv, rate / 1000);
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return rate;
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}
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static unsigned long clk_leafclk_recalc(struct clk *clk)
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{
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if (WARN_ON(!clk->parent))
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return clk->rate;
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pr_debug("%s: (parent %s) rate = %lu KHz\n",
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clk->name, clk->parent->name, clk->parent->rate / 1000);
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return clk->parent->rate;
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}
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static unsigned long clk_pllclk_recalc(struct clk *clk)
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{
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u32 ctrl, mult = 0, prediv = 0, postdiv = 0;
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u8 bypass;
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struct pll_data *pll = clk->pll_data;
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unsigned long rate = clk->rate;
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if (clk->flags & FIXED_RATE_PLL)
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return rate;
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ctrl = pll_read(pll, PLLCTL);
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rate = pll->input_rate = clk->parent->rate;
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if (ctrl & PLLCTL_PLLEN)
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bypass = 0;
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else
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bypass = 1;
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if (pll->flags & PLL_HAS_MUL) {
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mult = pll_read(pll, PLLM);
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mult = (mult & PLLM_PLLM_MASK) + 1;
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}
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if (pll->flags & PLL_HAS_PRE) {
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prediv = pll_read(pll, PLLPRE);
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if (prediv & PLLDIV_EN)
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prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
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else
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prediv = 0;
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}
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if (pll->flags & PLL_HAS_POST) {
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postdiv = pll_read(pll, PLLPOST);
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if (postdiv & PLLDIV_EN)
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postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
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else
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postdiv = 1;
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}
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if (!bypass) {
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if (prediv)
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rate /= prediv;
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if (mult)
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rate *= mult;
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if (postdiv)
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rate /= postdiv;
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pr_debug("PLL%d: input = %luMHz, pre[%d] mul[%d] post[%d] "
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"--> %luMHz output.\n",
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pll->num, clk->parent->rate / 1000000,
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prediv, mult, postdiv, rate / 1000000);
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} else
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pr_debug("PLL%d: input = %luMHz, bypass mode.\n",
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pll->num, clk->parent->rate / 1000000);
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return rate;
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}
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static void __init __init_clk(struct clk *clk)
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{
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INIT_LIST_HEAD(&clk->node);
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INIT_LIST_HEAD(&clk->children);
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INIT_LIST_HEAD(&clk->childnode);
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if (!clk->recalc) {
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/* Check if clock is a PLL */
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if (clk->pll_data)
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clk->recalc = clk_pllclk_recalc;
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/* Else, if it is a PLL-derived clock */
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else if (clk->flags & CLK_PLL)
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clk->recalc = clk_sysclk_recalc;
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/* Otherwise, it is a leaf clock (PSC clock) */
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else if (clk->parent)
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clk->recalc = clk_leafclk_recalc;
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}
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}
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void __init c6x_clks_init(struct clk_lookup *clocks)
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{
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struct clk_lookup *c;
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struct clk *clk;
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size_t num_clocks = 0;
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for (c = clocks; c->clk; c++) {
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clk = c->clk;
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__init_clk(clk);
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clk_register(clk);
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num_clocks++;
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/* Turn on clocks that Linux doesn't otherwise manage */
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if (clk->flags & ALWAYS_ENABLED)
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clk_enable(clk);
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}
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clkdev_add_table(clocks, num_clocks);
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}
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#ifdef CONFIG_DEBUG_FS
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#define CLKNAME_MAX 10 /* longest clock name */
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#define NEST_DELTA 2
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#define NEST_MAX 4
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static void
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dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
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{
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char *state;
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char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
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struct clk *clk;
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unsigned i;
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if (parent->flags & CLK_PLL)
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state = "pll";
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else
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state = "";
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/* <nest spaces> name <pad to end> */
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memset(buf, ' ', sizeof(buf) - 1);
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buf[sizeof(buf) - 1] = 0;
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i = strlen(parent->name);
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memcpy(buf + nest, parent->name,
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min(i, (unsigned)(sizeof(buf) - 1 - nest)));
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seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
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buf, parent->usecount, state, clk_get_rate(parent));
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/* REVISIT show device associations too */
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/* cost is now small, but not linear... */
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list_for_each_entry(clk, &parent->children, childnode) {
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dump_clock(s, nest + NEST_DELTA, clk);
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}
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}
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static int c6x_ck_show(struct seq_file *m, void *v)
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{
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struct clk *clk;
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/*
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* Show clock tree; We trust nonzero usecounts equate to PSC enables...
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*/
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mutex_lock(&clocks_mutex);
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list_for_each_entry(clk, &clocks, node)
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if (!clk->parent)
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dump_clock(m, 0, clk);
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mutex_unlock(&clocks_mutex);
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return 0;
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}
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static int c6x_ck_open(struct inode *inode, struct file *file)
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{
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return single_open(file, c6x_ck_show, NULL);
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}
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static const struct file_operations c6x_ck_operations = {
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.open = c6x_ck_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init c6x_clk_debugfs_init(void)
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{
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debugfs_create_file("c6x_clocks", S_IFREG | S_IRUGO, NULL, NULL,
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&c6x_ck_operations);
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return 0;
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}
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device_initcall(c6x_clk_debugfs_init);
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#endif /* CONFIG_DEBUG_FS */
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