871 lines
26 KiB
C
871 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/machine.h>
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#include <linux/regulator/pfuze100.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/regmap.h>
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#define PFUZE_FLAG_DISABLE_SW BIT(1)
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#define PFUZE_NUMREGS 128
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#define PFUZE100_VOL_OFFSET 0
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#define PFUZE100_STANDBY_OFFSET 1
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#define PFUZE100_MODE_OFFSET 3
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#define PFUZE100_CONF_OFFSET 4
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#define PFUZE100_DEVICEID 0x0
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#define PFUZE100_REVID 0x3
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#define PFUZE100_FABID 0x4
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#define PFUZE100_COINVOL 0x1a
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#define PFUZE100_SW1ABVOL 0x20
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#define PFUZE100_SW1ABMODE 0x23
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#define PFUZE100_SW1CVOL 0x2e
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#define PFUZE100_SW1CMODE 0x31
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#define PFUZE100_SW2VOL 0x35
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#define PFUZE100_SW2MODE 0x38
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#define PFUZE100_SW3AVOL 0x3c
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#define PFUZE100_SW3AMODE 0x3f
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#define PFUZE100_SW3BVOL 0x43
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#define PFUZE100_SW3BMODE 0x46
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#define PFUZE100_SW4VOL 0x4a
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#define PFUZE100_SW4MODE 0x4d
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#define PFUZE100_SWBSTCON1 0x66
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#define PFUZE100_VREFDDRCON 0x6a
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#define PFUZE100_VSNVSVOL 0x6b
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#define PFUZE100_VGEN1VOL 0x6c
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#define PFUZE100_VGEN2VOL 0x6d
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#define PFUZE100_VGEN3VOL 0x6e
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#define PFUZE100_VGEN4VOL 0x6f
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#define PFUZE100_VGEN5VOL 0x70
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#define PFUZE100_VGEN6VOL 0x71
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#define PFUZE100_SWxMODE_MASK 0xf
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#define PFUZE100_SWxMODE_APS_APS 0x8
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#define PFUZE100_SWxMODE_APS_OFF 0x4
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#define PFUZE100_VGENxLPWR BIT(6)
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#define PFUZE100_VGENxSTBY BIT(5)
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enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
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struct pfuze_regulator {
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struct regulator_desc desc;
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unsigned char stby_reg;
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unsigned char stby_mask;
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bool sw_reg;
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};
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struct pfuze_chip {
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int chip_id;
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int flags;
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struct regmap *regmap;
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struct device *dev;
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struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
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struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
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struct pfuze_regulator *pfuze_regulators;
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};
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static const int pfuze100_swbst[] = {
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5000000, 5050000, 5100000, 5150000,
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};
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static const int pfuze100_vsnvs[] = {
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1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
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};
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static const int pfuze100_coin[] = {
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2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
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};
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static const int pfuze3000_sw1a[] = {
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700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
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900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
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1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
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1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
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};
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static const int pfuze3000_sw2lo[] = {
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1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
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};
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static const int pfuze3000_sw2hi[] = {
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2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
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};
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static const struct i2c_device_id pfuze_device_id[] = {
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{.name = "pfuze100", .driver_data = PFUZE100},
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{.name = "pfuze200", .driver_data = PFUZE200},
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{.name = "pfuze3000", .driver_data = PFUZE3000},
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{.name = "pfuze3001", .driver_data = PFUZE3001},
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
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static const struct of_device_id pfuze_dt_ids[] = {
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{ .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
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{ .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
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{ .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
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{ .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
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{ }
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};
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MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
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static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
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{
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struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
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int id = rdev_get_id(rdev);
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bool reg_has_ramp_delay;
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unsigned int ramp_bits;
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int ret;
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switch (pfuze100->chip_id) {
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case PFUZE3001:
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/* no dynamic voltage scaling for PF3001 */
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reg_has_ramp_delay = false;
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break;
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case PFUZE3000:
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reg_has_ramp_delay = (id < PFUZE3000_SWBST);
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break;
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case PFUZE200:
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reg_has_ramp_delay = (id < PFUZE200_SWBST);
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break;
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case PFUZE100:
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default:
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reg_has_ramp_delay = (id < PFUZE100_SWBST);
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break;
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}
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if (reg_has_ramp_delay) {
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ramp_delay = 12500 / ramp_delay;
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ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
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ret = regmap_update_bits(pfuze100->regmap,
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rdev->desc->vsel_reg + 4,
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0xc0, ramp_bits << 6);
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if (ret < 0)
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dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
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} else {
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ret = -EACCES;
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}
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return ret;
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}
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static const struct regulator_ops pfuze100_ldo_regulator_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_linear,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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};
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static const struct regulator_ops pfuze100_fixed_regulator_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_linear,
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};
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static const struct regulator_ops pfuze100_sw_regulator_ops = {
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.list_voltage = regulator_list_voltage_linear,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_time_sel = regulator_set_voltage_time_sel,
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.set_ramp_delay = pfuze100_set_ramp_delay,
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};
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static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_linear,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_time_sel = regulator_set_voltage_time_sel,
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.set_ramp_delay = pfuze100_set_ramp_delay,
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};
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static const struct regulator_ops pfuze100_swb_regulator_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_table,
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.map_voltage = regulator_map_voltage_ascend,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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};
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#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
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[_chip ## _ ## _name] = { \
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.desc = { \
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.name = #_name, \
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.n_voltages = 1, \
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.ops = &pfuze100_fixed_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.min_uV = (voltage), \
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.enable_reg = (base), \
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.enable_mask = 0x10, \
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}, \
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}
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#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
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[_chip ## _ ## _name] = { \
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.desc = { \
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.name = #_name,\
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.ops = &pfuze100_sw_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.min_uV = (min), \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0x3f, \
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.enable_reg = (base) + PFUZE100_MODE_OFFSET, \
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.enable_mask = 0xf, \
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}, \
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.stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
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.stby_mask = 0x3f, \
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.sw_reg = true, \
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}
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#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
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[_chip ## _ ## _name] = { \
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.desc = { \
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.name = #_name, \
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.n_voltages = ARRAY_SIZE(voltages), \
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.ops = &pfuze100_swb_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.volt_table = voltages, \
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.vsel_reg = (base), \
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.vsel_mask = (mask), \
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.enable_reg = (base), \
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.enable_mask = 0x48, \
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}, \
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}
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#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
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[_chip ## _ ## _name] = { \
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.desc = { \
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.name = #_name, \
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.ops = &pfuze100_ldo_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.min_uV = (min), \
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.uV_step = (step), \
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.vsel_reg = (base), \
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.vsel_mask = 0xf, \
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.enable_reg = (base), \
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.enable_mask = 0x10, \
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}, \
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.stby_reg = (base), \
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.stby_mask = 0x20, \
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}
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#define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
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[_chip ## _ ## _name] = { \
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.desc = { \
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.name = #_name, \
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.n_voltages = ARRAY_SIZE(voltages), \
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.ops = &pfuze100_swb_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.volt_table = voltages, \
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.vsel_reg = (base), \
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.vsel_mask = (mask), \
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.enable_reg = (base), \
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.enable_mask = 0x8, \
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}, \
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}
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#define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
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.desc = { \
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.name = #_name, \
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.ops = &pfuze100_ldo_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.min_uV = (min), \
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.uV_step = (step), \
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.vsel_reg = (base), \
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.vsel_mask = 0x3, \
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.enable_reg = (base), \
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.enable_mask = 0x10, \
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}, \
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.stby_reg = (base), \
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.stby_mask = 0x20, \
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}
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#define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \
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.desc = { \
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.name = #_name,\
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.ops = &pfuze100_sw_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.min_uV = (min), \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0x7, \
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}, \
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.stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
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.stby_mask = 0x7, \
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}
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#define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
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.desc = { \
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.name = #_name,\
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.n_voltages = ((max) - (min)) / (step) + 1, \
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.ops = &pfuze100_sw_regulator_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = _chip ## _ ## _name, \
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.owner = THIS_MODULE, \
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.min_uV = (min), \
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.uV_step = (step), \
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.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
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.vsel_mask = 0xf, \
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}, \
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.stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
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.stby_mask = 0xf, \
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}
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/* PFUZE100 */
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static struct pfuze_regulator pfuze100_regulators[] = {
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PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
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PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
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PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
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PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
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PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
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PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
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PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
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PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
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PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
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PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
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PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
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PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
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PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
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PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
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PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
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PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
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};
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static struct pfuze_regulator pfuze200_regulators[] = {
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PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
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PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
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PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
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PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
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PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
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PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
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PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
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PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
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PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
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PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
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PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
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PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
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PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
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PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
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};
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static struct pfuze_regulator pfuze3000_regulators[] = {
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PFUZE100_SWB_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
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PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
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PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
|
|
PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
|
|
PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
|
|
PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
|
|
PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
|
|
PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
|
|
PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
|
|
PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
|
|
PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
|
|
PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
|
|
PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
|
|
};
|
|
|
|
static struct pfuze_regulator pfuze3001_regulators[] = {
|
|
PFUZE100_SWB_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
|
|
PFUZE100_SWB_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
|
|
PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
|
|
PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
|
|
PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
|
|
PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
|
|
PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
|
|
PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
|
|
PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
|
|
PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
|
|
};
|
|
|
|
#ifdef CONFIG_OF
|
|
/* PFUZE100 */
|
|
static struct of_regulator_match pfuze100_matches[] = {
|
|
{ .name = "sw1ab", },
|
|
{ .name = "sw1c", },
|
|
{ .name = "sw2", },
|
|
{ .name = "sw3a", },
|
|
{ .name = "sw3b", },
|
|
{ .name = "sw4", },
|
|
{ .name = "swbst", },
|
|
{ .name = "vsnvs", },
|
|
{ .name = "vrefddr", },
|
|
{ .name = "vgen1", },
|
|
{ .name = "vgen2", },
|
|
{ .name = "vgen3", },
|
|
{ .name = "vgen4", },
|
|
{ .name = "vgen5", },
|
|
{ .name = "vgen6", },
|
|
{ .name = "coin", },
|
|
};
|
|
|
|
/* PFUZE200 */
|
|
static struct of_regulator_match pfuze200_matches[] = {
|
|
|
|
{ .name = "sw1ab", },
|
|
{ .name = "sw2", },
|
|
{ .name = "sw3a", },
|
|
{ .name = "sw3b", },
|
|
{ .name = "swbst", },
|
|
{ .name = "vsnvs", },
|
|
{ .name = "vrefddr", },
|
|
{ .name = "vgen1", },
|
|
{ .name = "vgen2", },
|
|
{ .name = "vgen3", },
|
|
{ .name = "vgen4", },
|
|
{ .name = "vgen5", },
|
|
{ .name = "vgen6", },
|
|
{ .name = "coin", },
|
|
};
|
|
|
|
/* PFUZE3000 */
|
|
static struct of_regulator_match pfuze3000_matches[] = {
|
|
|
|
{ .name = "sw1a", },
|
|
{ .name = "sw1b", },
|
|
{ .name = "sw2", },
|
|
{ .name = "sw3", },
|
|
{ .name = "swbst", },
|
|
{ .name = "vsnvs", },
|
|
{ .name = "vrefddr", },
|
|
{ .name = "vldo1", },
|
|
{ .name = "vldo2", },
|
|
{ .name = "vccsd", },
|
|
{ .name = "v33", },
|
|
{ .name = "vldo3", },
|
|
{ .name = "vldo4", },
|
|
};
|
|
|
|
/* PFUZE3001 */
|
|
static struct of_regulator_match pfuze3001_matches[] = {
|
|
|
|
{ .name = "sw1", },
|
|
{ .name = "sw2", },
|
|
{ .name = "sw3", },
|
|
{ .name = "vsnvs", },
|
|
{ .name = "vldo1", },
|
|
{ .name = "vldo2", },
|
|
{ .name = "vccsd", },
|
|
{ .name = "v33", },
|
|
{ .name = "vldo3", },
|
|
{ .name = "vldo4", },
|
|
};
|
|
|
|
static struct of_regulator_match *pfuze_matches;
|
|
|
|
static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
|
|
{
|
|
struct device *dev = chip->dev;
|
|
struct device_node *np, *parent;
|
|
int ret;
|
|
|
|
np = of_node_get(dev->of_node);
|
|
if (!np)
|
|
return -EINVAL;
|
|
|
|
if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
|
|
chip->flags |= PFUZE_FLAG_DISABLE_SW;
|
|
|
|
parent = of_get_child_by_name(np, "regulators");
|
|
if (!parent) {
|
|
dev_err(dev, "regulators node not found\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (chip->chip_id) {
|
|
case PFUZE3001:
|
|
pfuze_matches = pfuze3001_matches;
|
|
ret = of_regulator_match(dev, parent, pfuze3001_matches,
|
|
ARRAY_SIZE(pfuze3001_matches));
|
|
break;
|
|
case PFUZE3000:
|
|
pfuze_matches = pfuze3000_matches;
|
|
ret = of_regulator_match(dev, parent, pfuze3000_matches,
|
|
ARRAY_SIZE(pfuze3000_matches));
|
|
break;
|
|
case PFUZE200:
|
|
pfuze_matches = pfuze200_matches;
|
|
ret = of_regulator_match(dev, parent, pfuze200_matches,
|
|
ARRAY_SIZE(pfuze200_matches));
|
|
break;
|
|
|
|
case PFUZE100:
|
|
default:
|
|
pfuze_matches = pfuze100_matches;
|
|
ret = of_regulator_match(dev, parent, pfuze100_matches,
|
|
ARRAY_SIZE(pfuze100_matches));
|
|
break;
|
|
}
|
|
|
|
of_node_put(parent);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Error parsing regulator init data: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline struct regulator_init_data *match_init_data(int index)
|
|
{
|
|
return pfuze_matches[index].init_data;
|
|
}
|
|
|
|
static inline struct device_node *match_of_node(int index)
|
|
{
|
|
return pfuze_matches[index].of_node;
|
|
}
|
|
#else
|
|
static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline struct regulator_init_data *match_init_data(int index)
|
|
{
|
|
return NULL;
|
|
}
|
|
|
|
static inline struct device_node *match_of_node(int index)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
static struct pfuze_chip *syspm_pfuze_chip;
|
|
|
|
static void pfuze_power_off_prepare(void)
|
|
{
|
|
dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
|
|
|
|
/* Switch from default mode: APS/APS to APS/Off */
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
|
|
PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
|
|
PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
|
|
PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
|
|
PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
|
|
PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
|
|
PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
|
|
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
|
|
PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
|
|
PFUZE100_VGENxSTBY);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
|
|
PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
|
|
PFUZE100_VGENxSTBY);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
|
|
PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
|
|
PFUZE100_VGENxSTBY);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
|
|
PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
|
|
PFUZE100_VGENxSTBY);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
|
|
PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
|
|
PFUZE100_VGENxSTBY);
|
|
regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
|
|
PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
|
|
PFUZE100_VGENxSTBY);
|
|
}
|
|
|
|
static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
|
|
{
|
|
if (pfuze_chip->chip_id != PFUZE100) {
|
|
dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (pm_power_off_prepare) {
|
|
dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (syspm_pfuze_chip) {
|
|
dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
syspm_pfuze_chip = pfuze_chip;
|
|
pm_power_off_prepare = pfuze_power_off_prepare;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pfuze_identify(struct pfuze_chip *pfuze_chip)
|
|
{
|
|
unsigned int value;
|
|
int ret;
|
|
|
|
ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
|
|
/*
|
|
* Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
|
|
* as ID=8 in PFUZE100
|
|
*/
|
|
dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
|
|
} else if ((value & 0x0f) != pfuze_chip->chip_id &&
|
|
(value & 0xf0) >> 4 != pfuze_chip->chip_id &&
|
|
(value != pfuze_chip->chip_id)) {
|
|
/* device id NOT match with your setting */
|
|
dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
|
|
return -ENODEV;
|
|
}
|
|
|
|
ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
|
|
if (ret)
|
|
return ret;
|
|
dev_info(pfuze_chip->dev,
|
|
"Full layer: %x, Metal layer: %x\n",
|
|
(value & 0xf0) >> 4, value & 0x0f);
|
|
|
|
ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
|
|
if (ret)
|
|
return ret;
|
|
dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
|
|
(value & 0xc) >> 2, value & 0x3);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct regmap_config pfuze_regmap_config = {
|
|
.reg_bits = 8,
|
|
.val_bits = 8,
|
|
.max_register = PFUZE_NUMREGS - 1,
|
|
.cache_type = REGCACHE_RBTREE,
|
|
};
|
|
|
|
static int pfuze100_regulator_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct pfuze_chip *pfuze_chip;
|
|
struct pfuze_regulator_platform_data *pdata =
|
|
dev_get_platdata(&client->dev);
|
|
struct regulator_config config = { };
|
|
int i, ret;
|
|
const struct of_device_id *match;
|
|
u32 regulator_num;
|
|
u32 sw_check_start, sw_check_end, sw_hi = 0x40;
|
|
|
|
pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
|
|
GFP_KERNEL);
|
|
if (!pfuze_chip)
|
|
return -ENOMEM;
|
|
|
|
if (client->dev.of_node) {
|
|
match = of_match_device(of_match_ptr(pfuze_dt_ids),
|
|
&client->dev);
|
|
if (!match) {
|
|
dev_err(&client->dev, "Error: No device match found\n");
|
|
return -ENODEV;
|
|
}
|
|
pfuze_chip->chip_id = (int)(long)match->data;
|
|
} else if (id) {
|
|
pfuze_chip->chip_id = id->driver_data;
|
|
} else {
|
|
dev_err(&client->dev, "No dts match or id table match found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
i2c_set_clientdata(client, pfuze_chip);
|
|
pfuze_chip->dev = &client->dev;
|
|
|
|
pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
|
|
if (IS_ERR(pfuze_chip->regmap)) {
|
|
ret = PTR_ERR(pfuze_chip->regmap);
|
|
dev_err(&client->dev,
|
|
"regmap allocation failed with err %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = pfuze_identify(pfuze_chip);
|
|
if (ret) {
|
|
dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
|
|
return ret;
|
|
}
|
|
|
|
/* use the right regulators after identify the right device */
|
|
switch (pfuze_chip->chip_id) {
|
|
case PFUZE3001:
|
|
pfuze_chip->pfuze_regulators = pfuze3001_regulators;
|
|
regulator_num = ARRAY_SIZE(pfuze3001_regulators);
|
|
sw_check_start = PFUZE3001_SW2;
|
|
sw_check_end = PFUZE3001_SW2;
|
|
sw_hi = 1 << 3;
|
|
break;
|
|
case PFUZE3000:
|
|
pfuze_chip->pfuze_regulators = pfuze3000_regulators;
|
|
regulator_num = ARRAY_SIZE(pfuze3000_regulators);
|
|
sw_check_start = PFUZE3000_SW2;
|
|
sw_check_end = PFUZE3000_SW2;
|
|
sw_hi = 1 << 3;
|
|
break;
|
|
case PFUZE200:
|
|
pfuze_chip->pfuze_regulators = pfuze200_regulators;
|
|
regulator_num = ARRAY_SIZE(pfuze200_regulators);
|
|
sw_check_start = PFUZE200_SW2;
|
|
sw_check_end = PFUZE200_SW3B;
|
|
break;
|
|
case PFUZE100:
|
|
default:
|
|
pfuze_chip->pfuze_regulators = pfuze100_regulators;
|
|
regulator_num = ARRAY_SIZE(pfuze100_regulators);
|
|
sw_check_start = PFUZE100_SW2;
|
|
sw_check_end = PFUZE100_SW4;
|
|
break;
|
|
}
|
|
dev_info(&client->dev, "pfuze%s found.\n",
|
|
(pfuze_chip->chip_id == PFUZE100) ? "100" :
|
|
(((pfuze_chip->chip_id == PFUZE200) ? "200" :
|
|
((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
|
|
|
|
memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
|
|
sizeof(pfuze_chip->regulator_descs));
|
|
|
|
ret = pfuze_parse_regulators_dt(pfuze_chip);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < regulator_num; i++) {
|
|
struct regulator_init_data *init_data;
|
|
struct regulator_desc *desc;
|
|
int val;
|
|
|
|
desc = &pfuze_chip->regulator_descs[i].desc;
|
|
|
|
if (pdata)
|
|
init_data = pdata->init_data[i];
|
|
else
|
|
init_data = match_init_data(i);
|
|
|
|
/* SW2~SW4 high bit check and modify the voltage value table */
|
|
if (i >= sw_check_start && i <= sw_check_end) {
|
|
ret = regmap_read(pfuze_chip->regmap,
|
|
desc->vsel_reg, &val);
|
|
if (ret) {
|
|
dev_err(&client->dev, "Fails to read from the register.\n");
|
|
return ret;
|
|
}
|
|
|
|
if (val & sw_hi) {
|
|
if (pfuze_chip->chip_id == PFUZE3000 ||
|
|
pfuze_chip->chip_id == PFUZE3001) {
|
|
desc->volt_table = pfuze3000_sw2hi;
|
|
desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
|
|
} else {
|
|
desc->min_uV = 800000;
|
|
desc->uV_step = 50000;
|
|
desc->n_voltages = 51;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Allow SW regulators to turn off. Checking it trough a flag is
|
|
* a workaround to keep the backward compatibility with existing
|
|
* old dtb's which may relay on the fact that we didn't disable
|
|
* the switched regulator till yet.
|
|
*/
|
|
if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
|
|
if (pfuze_chip->regulator_descs[i].sw_reg) {
|
|
desc->ops = &pfuze100_sw_disable_regulator_ops;
|
|
desc->enable_val = 0x8;
|
|
desc->disable_val = 0x0;
|
|
desc->enable_time = 500;
|
|
}
|
|
}
|
|
|
|
config.dev = &client->dev;
|
|
config.init_data = init_data;
|
|
config.driver_data = pfuze_chip;
|
|
config.of_node = match_of_node(i);
|
|
|
|
pfuze_chip->regulators[i] =
|
|
devm_regulator_register(&client->dev, desc, &config);
|
|
if (IS_ERR(pfuze_chip->regulators[i])) {
|
|
dev_err(&client->dev, "register regulator%s failed\n",
|
|
pfuze_chip->pfuze_regulators[i].desc.name);
|
|
return PTR_ERR(pfuze_chip->regulators[i]);
|
|
}
|
|
}
|
|
|
|
if (of_property_read_bool(client->dev.of_node,
|
|
"fsl,pmic-stby-poweroff"))
|
|
return pfuze_power_off_prepare_init(pfuze_chip);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pfuze100_regulator_remove(struct i2c_client *client)
|
|
{
|
|
if (syspm_pfuze_chip) {
|
|
syspm_pfuze_chip = NULL;
|
|
pm_power_off_prepare = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct i2c_driver pfuze_driver = {
|
|
.id_table = pfuze_device_id,
|
|
.driver = {
|
|
.name = "pfuze100-regulator",
|
|
.of_match_table = pfuze_dt_ids,
|
|
},
|
|
.probe = pfuze100_regulator_probe,
|
|
.remove = pfuze100_regulator_remove,
|
|
};
|
|
module_i2c_driver(pfuze_driver);
|
|
|
|
MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
|
|
MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
|
|
MODULE_LICENSE("GPL v2");
|