563 lines
14 KiB
C
563 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Atom SOC Power Management Controller Driver
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* Copyright (c) 2014, Intel Corporation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/dmi.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_data/x86/clk-pmc-atom.h>
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#include <linux/platform_data/x86/pmc_atom.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/seq_file.h>
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struct pmc_bit_map {
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const char *name;
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u32 bit_mask;
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};
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struct pmc_reg_map {
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const struct pmc_bit_map *d3_sts_0;
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const struct pmc_bit_map *d3_sts_1;
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const struct pmc_bit_map *func_dis;
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const struct pmc_bit_map *func_dis_2;
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const struct pmc_bit_map *pss;
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};
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struct pmc_data {
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const struct pmc_reg_map *map;
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const struct pmc_clk *clks;
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};
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struct pmc_dev {
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u32 base_addr;
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void __iomem *regmap;
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const struct pmc_reg_map *map;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dbgfs_dir;
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#endif /* CONFIG_DEBUG_FS */
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bool init;
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};
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static struct pmc_dev pmc_device;
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static u32 acpi_base_addr;
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static const struct pmc_clk byt_clks[] = {
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{
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.name = "xtal",
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.freq = 25000000,
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.parent_name = NULL,
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},
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{
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.name = "pll",
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.freq = 19200000,
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.parent_name = "xtal",
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},
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{},
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};
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static const struct pmc_clk cht_clks[] = {
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{
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.name = "xtal",
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.freq = 19200000,
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.parent_name = NULL,
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},
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{},
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};
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static const struct pmc_bit_map d3_sts_0_map[] = {
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{"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
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{"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
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{"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
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{"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
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{"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
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{"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
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{"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
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{"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
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{"SCC_EMMC", BIT_SCC_EMMC},
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{"SCC_SDIO", BIT_SCC_SDIO},
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{"SCC_SDCARD", BIT_SCC_SDCARD},
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{"SCC_MIPI", BIT_SCC_MIPI},
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{"HDA", BIT_HDA},
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{"LPE", BIT_LPE},
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{"OTG", BIT_OTG},
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{"USH", BIT_USH},
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{"GBE", BIT_GBE},
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{"SATA", BIT_SATA},
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{"USB_EHCI", BIT_USB_EHCI},
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{"SEC", BIT_SEC},
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{"PCIE_PORT0", BIT_PCIE_PORT0},
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{"PCIE_PORT1", BIT_PCIE_PORT1},
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{"PCIE_PORT2", BIT_PCIE_PORT2},
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{"PCIE_PORT3", BIT_PCIE_PORT3},
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{"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
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{"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
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{"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
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{"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
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{"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
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{"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
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{"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
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{"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
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{},
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};
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static struct pmc_bit_map byt_d3_sts_1_map[] = {
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{"SMB", BIT_SMB},
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{"OTG_SS_PHY", BIT_OTG_SS_PHY},
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{"USH_SS_PHY", BIT_USH_SS_PHY},
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{"DFX", BIT_DFX},
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{},
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};
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static struct pmc_bit_map cht_d3_sts_1_map[] = {
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{"SMB", BIT_SMB},
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{"GMM", BIT_STS_GMM},
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{"ISH", BIT_STS_ISH},
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{},
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};
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static struct pmc_bit_map cht_func_dis_2_map[] = {
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{"SMB", BIT_SMB},
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{"GMM", BIT_FD_GMM},
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{"ISH", BIT_FD_ISH},
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{},
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};
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static const struct pmc_bit_map byt_pss_map[] = {
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{"GBE", PMC_PSS_BIT_GBE},
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{"SATA", PMC_PSS_BIT_SATA},
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{"HDA", PMC_PSS_BIT_HDA},
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{"SEC", PMC_PSS_BIT_SEC},
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{"PCIE", PMC_PSS_BIT_PCIE},
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{"LPSS", PMC_PSS_BIT_LPSS},
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{"LPE", PMC_PSS_BIT_LPE},
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{"DFX", PMC_PSS_BIT_DFX},
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{"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
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{"USH_SUS", PMC_PSS_BIT_USH_SUS},
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{"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
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{"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
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{"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
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{"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
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{"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
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{"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
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{"USB", PMC_PSS_BIT_USB},
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{"USB_SUS", PMC_PSS_BIT_USB_SUS},
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{},
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};
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static const struct pmc_bit_map cht_pss_map[] = {
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{"SATA", PMC_PSS_BIT_SATA},
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{"HDA", PMC_PSS_BIT_HDA},
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{"SEC", PMC_PSS_BIT_SEC},
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{"PCIE", PMC_PSS_BIT_PCIE},
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{"LPSS", PMC_PSS_BIT_LPSS},
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{"LPE", PMC_PSS_BIT_LPE},
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{"UFS", PMC_PSS_BIT_CHT_UFS},
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{"UXD", PMC_PSS_BIT_CHT_UXD},
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{"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
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{"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
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{"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
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{"GMM", PMC_PSS_BIT_CHT_GMM},
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{"ISH", PMC_PSS_BIT_CHT_ISH},
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{"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
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{"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
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{"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
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{"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
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{"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
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{"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
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{},
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};
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static const struct pmc_reg_map byt_reg_map = {
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.d3_sts_0 = d3_sts_0_map,
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.d3_sts_1 = byt_d3_sts_1_map,
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.func_dis = d3_sts_0_map,
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.func_dis_2 = byt_d3_sts_1_map,
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.pss = byt_pss_map,
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};
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static const struct pmc_reg_map cht_reg_map = {
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.d3_sts_0 = d3_sts_0_map,
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.d3_sts_1 = cht_d3_sts_1_map,
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.func_dis = d3_sts_0_map,
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.func_dis_2 = cht_func_dis_2_map,
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.pss = cht_pss_map,
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};
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static const struct pmc_data byt_data = {
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.map = &byt_reg_map,
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.clks = byt_clks,
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};
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static const struct pmc_data cht_data = {
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.map = &cht_reg_map,
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.clks = cht_clks,
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};
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static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
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{
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return readl(pmc->regmap + reg_offset);
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}
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static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
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{
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writel(val, pmc->regmap + reg_offset);
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}
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int pmc_atom_read(int offset, u32 *value)
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{
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struct pmc_dev *pmc = &pmc_device;
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if (!pmc->init)
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return -ENODEV;
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*value = pmc_reg_read(pmc, offset);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pmc_atom_read);
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int pmc_atom_write(int offset, u32 value)
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{
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struct pmc_dev *pmc = &pmc_device;
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if (!pmc->init)
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return -ENODEV;
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pmc_reg_write(pmc, offset, value);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pmc_atom_write);
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static void pmc_power_off(void)
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{
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u16 pm1_cnt_port;
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u32 pm1_cnt_value;
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pr_info("Preparing to enter system sleep state S5\n");
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pm1_cnt_port = acpi_base_addr + PM1_CNT;
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pm1_cnt_value = inl(pm1_cnt_port);
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pm1_cnt_value &= SLEEP_TYPE_MASK;
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pm1_cnt_value |= SLEEP_TYPE_S5;
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pm1_cnt_value |= SLEEP_ENABLE;
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outl(pm1_cnt_value, pm1_cnt_port);
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}
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static void pmc_hw_reg_setup(struct pmc_dev *pmc)
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{
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/*
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* Disable PMC S0IX_WAKE_EN events coming from:
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* - LPC clock run
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* - GPIO_SUS ored dedicated IRQs
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* - GPIO_SCORE ored dedicated IRQs
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* - GPIO_SUS shared IRQ
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* - GPIO_SCORE shared IRQ
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*/
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pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
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}
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#ifdef CONFIG_DEBUG_FS
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static void pmc_dev_state_print(struct seq_file *s, int reg_index,
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u32 sts, const struct pmc_bit_map *sts_map,
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u32 fd, const struct pmc_bit_map *fd_map)
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{
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int offset = PMC_REG_BIT_WIDTH * reg_index;
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int index;
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for (index = 0; sts_map[index].name; index++) {
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seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
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offset + index, sts_map[index].name,
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fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
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sts_map[index].bit_mask & sts ? "D3" : "D0");
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}
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}
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static int pmc_dev_state_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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const struct pmc_reg_map *m = pmc->map;
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u32 func_dis, func_dis_2;
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u32 d3_sts_0, d3_sts_1;
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func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
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func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
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d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
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d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
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/* Low part */
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pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
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/* High part */
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pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
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static int pmc_pss_state_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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const struct pmc_bit_map *map = pmc->map->pss;
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u32 pss = pmc_reg_read(pmc, PMC_PSS);
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int index;
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for (index = 0; map[index].name; index++) {
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seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
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index, map[index].name,
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map[index].bit_mask & pss ? "Off" : "On");
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
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static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
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{
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struct pmc_dev *pmc = s->private;
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u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
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s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
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s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
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s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
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s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
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s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
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seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
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seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
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seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
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seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
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seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
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static void pmc_dbgfs_register(struct pmc_dev *pmc)
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{
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struct dentry *dir;
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dir = debugfs_create_dir("pmc_atom", NULL);
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pmc->dbgfs_dir = dir;
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debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc,
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&pmc_dev_state_fops);
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debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc,
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&pmc_pss_state_fops);
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debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc,
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&pmc_sleep_tmr_fops);
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}
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#else
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static void pmc_dbgfs_register(struct pmc_dev *pmc)
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{
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}
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#endif /* CONFIG_DEBUG_FS */
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/*
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* Some systems need one or more of their pmc_plt_clks to be
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* marked as critical.
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*/
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static const struct dmi_system_id critclk_systems[] = {
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{
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/* pmc_plt_clk0 is used for an external HSIC USB HUB */
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.ident = "MPL CEC1x",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
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DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
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},
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},
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{
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/* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */
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.ident = "Lex 3I380D",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
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DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"),
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},
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},
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{
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/* pmc_plt_clk* - are used for ethernet controllers */
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.ident = "Lex 2I385SW",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
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DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"),
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},
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},
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{
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/* pmc_plt_clk* - are used for ethernet controllers */
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.ident = "Beckhoff CB3163",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
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DMI_MATCH(DMI_BOARD_NAME, "CB3163"),
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},
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},
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{
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/* pmc_plt_clk* - are used for ethernet controllers */
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.ident = "Beckhoff CB4063",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
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DMI_MATCH(DMI_BOARD_NAME, "CB4063"),
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},
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},
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{
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/* pmc_plt_clk* - are used for ethernet controllers */
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.ident = "Beckhoff CB6263",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
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DMI_MATCH(DMI_BOARD_NAME, "CB6263"),
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},
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},
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{
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/* pmc_plt_clk* - are used for ethernet controllers */
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.ident = "Beckhoff CB6363",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
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DMI_MATCH(DMI_BOARD_NAME, "CB6363"),
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},
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},
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{
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.ident = "SIMATIC IPC227E",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "6ES7647-8B"),
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},
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},
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{
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.ident = "SIMATIC IPC277E",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
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DMI_MATCH(DMI_PRODUCT_VERSION, "6AV7882-0"),
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},
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},
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{
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.ident = "CONNECT X300",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
|
|
DMI_MATCH(DMI_PRODUCT_VERSION, "A5E45074588"),
|
|
},
|
|
},
|
|
|
|
{ /*sentinel*/ }
|
|
};
|
|
|
|
static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
|
|
const struct pmc_data *pmc_data)
|
|
{
|
|
struct platform_device *clkdev;
|
|
struct pmc_clk_data *clk_data;
|
|
const struct dmi_system_id *d = dmi_first_match(critclk_systems);
|
|
|
|
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
|
|
if (!clk_data)
|
|
return -ENOMEM;
|
|
|
|
clk_data->base = pmc_regmap; /* offset is added by client */
|
|
clk_data->clks = pmc_data->clks;
|
|
if (d) {
|
|
clk_data->critical = true;
|
|
pr_info("%s critclks quirk enabled\n", d->ident);
|
|
}
|
|
|
|
clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
|
|
PLATFORM_DEVID_NONE,
|
|
clk_data, sizeof(*clk_data));
|
|
if (IS_ERR(clkdev)) {
|
|
kfree(clk_data);
|
|
return PTR_ERR(clkdev);
|
|
}
|
|
|
|
kfree(clk_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
{
|
|
struct pmc_dev *pmc = &pmc_device;
|
|
const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
|
|
const struct pmc_reg_map *map = data->map;
|
|
int ret;
|
|
|
|
/* Obtain ACPI base address */
|
|
pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
|
|
acpi_base_addr &= ACPI_BASE_ADDR_MASK;
|
|
|
|
/* Install power off function */
|
|
if (acpi_base_addr != 0 && pm_power_off == NULL)
|
|
pm_power_off = pmc_power_off;
|
|
|
|
pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
|
|
pmc->base_addr &= PMC_BASE_ADDR_MASK;
|
|
|
|
pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
|
|
if (!pmc->regmap) {
|
|
dev_err(&pdev->dev, "error: ioremap failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pmc->map = map;
|
|
|
|
/* PMC hardware registers setup */
|
|
pmc_hw_reg_setup(pmc);
|
|
|
|
pmc_dbgfs_register(pmc);
|
|
|
|
/* Register platform clocks - PMC_PLT_CLK [0..5] */
|
|
ret = pmc_setup_clks(pdev, pmc->regmap, data);
|
|
if (ret)
|
|
dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
|
|
ret);
|
|
|
|
pmc->init = true;
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Data for PCI driver interface
|
|
*
|
|
* used by pci_match_id() call below.
|
|
*/
|
|
static const struct pci_device_id pmc_pci_ids[] = {
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
|
|
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
|
|
{ 0, },
|
|
};
|
|
|
|
static int __init pmc_atom_init(void)
|
|
{
|
|
struct pci_dev *pdev = NULL;
|
|
const struct pci_device_id *ent;
|
|
|
|
/* We look for our device - PCU PMC
|
|
* we assume that there is max. one device.
|
|
*
|
|
* We can't use plain pci_driver mechanism,
|
|
* as the device is really a multiple function device,
|
|
* main driver that binds to the pci_device is lpc_ich
|
|
* and have to find & bind to the device this way.
|
|
*/
|
|
for_each_pci_dev(pdev) {
|
|
ent = pci_match_id(pmc_pci_ids, pdev);
|
|
if (ent)
|
|
return pmc_setup_dev(pdev, ent);
|
|
}
|
|
/* Device not found. */
|
|
return -ENODEV;
|
|
}
|
|
|
|
device_initcall(pmc_atom_init);
|
|
|
|
/*
|
|
MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
|
|
MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
|
|
MODULE_LICENSE("GPL v2");
|
|
*/
|