350 lines
12 KiB
C
350 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* http://www.linaro.org
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*
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*/
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#ifndef __PINCTRL_SAMSUNG_H
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#define __PINCTRL_SAMSUNG_H
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/gpio/driver.h>
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/**
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* enum pincfg_type - possible pin configuration types supported.
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* @PINCFG_TYPE_FUNC: Function configuration.
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* @PINCFG_TYPE_DAT: Pin value configuration.
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* @PINCFG_TYPE_PUD: Pull up/down configuration.
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* @PINCFG_TYPE_DRV: Drive strength configuration.
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* @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
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* @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
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*/
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enum pincfg_type {
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PINCFG_TYPE_FUNC,
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PINCFG_TYPE_DAT,
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PINCFG_TYPE_PUD,
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PINCFG_TYPE_DRV,
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PINCFG_TYPE_CON_PDN,
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PINCFG_TYPE_PUD_PDN,
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PINCFG_TYPE_NUM
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};
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/*
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* pin configuration (pull up/down and drive strength) type and its value are
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* packed together into a 16-bits. The upper 8-bits represent the configuration
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* type and the lower 8-bits hold the value of the configuration type.
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*/
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#define PINCFG_TYPE_MASK 0xFF
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#define PINCFG_VALUE_SHIFT 8
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#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
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#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
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#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
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#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
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PINCFG_VALUE_SHIFT)
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/**
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* enum eint_type - possible external interrupt types.
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* @EINT_TYPE_NONE: bank does not support external interrupts
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* @EINT_TYPE_GPIO: bank supportes external gpio interrupts
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* @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
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* @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
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*
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* Samsung GPIO controller groups all the available pins into banks. The pins
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* in a pin bank can support external gpio interrupts or external wakeup
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* interrupts or no interrupts at all. From a software perspective, the only
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* difference between external gpio and external wakeup interrupts is that
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* the wakeup interrupts can additionally wakeup the system if it is in
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* suspended state.
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*/
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enum eint_type {
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EINT_TYPE_NONE,
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EINT_TYPE_GPIO,
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EINT_TYPE_WKUP,
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EINT_TYPE_WKUP_MUX,
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};
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/* maximum length of a pin in pin descriptor (example: "gpa0-0") */
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#define PIN_NAME_LENGTH 10
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#define PIN_GROUP(n, p, f) \
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{ \
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.name = n, \
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.pins = p, \
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.num_pins = ARRAY_SIZE(p), \
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.func = f \
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}
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#define PMX_FUNC(n, g) \
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{ \
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.name = n, \
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.groups = g, \
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.num_groups = ARRAY_SIZE(g), \
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}
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struct samsung_pinctrl_drv_data;
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/**
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* struct samsung_pin_bank_type: pin bank type description
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* @fld_width: widths of configuration bitfields (0 if unavailable)
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* @reg_offset: offsets of configuration registers (don't care of width is 0)
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*/
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struct samsung_pin_bank_type {
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u8 fld_width[PINCFG_TYPE_NUM];
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u8 reg_offset[PINCFG_TYPE_NUM];
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};
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/**
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* struct samsung_pin_bank_data: represent a controller pin-bank (init data).
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* @type: type of the bank (register offsets and bitfield widths)
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* @pctl_offset: starting offset of the pin-bank registers.
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* @pctl_res_idx: index of base address for pin-bank registers.
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* @nr_pins: number of pins included in this bank.
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* @eint_func: function to set in CON register to configure pin as EINT.
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* @eint_type: type of the external interrupt supported by the bank.
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* @eint_mask: bit mask of pins which support EINT function.
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* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
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* @name: name to be prefixed for each pin in this pin bank.
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*/
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struct samsung_pin_bank_data {
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const struct samsung_pin_bank_type *type;
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u32 pctl_offset;
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u8 pctl_res_idx;
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u8 nr_pins;
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u8 eint_func;
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enum eint_type eint_type;
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u32 eint_mask;
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u32 eint_offset;
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const char *name;
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};
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/**
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* struct samsung_pin_bank: represent a controller pin-bank.
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* @type: type of the bank (register offsets and bitfield widths)
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* @pctl_base: base address of the pin-bank registers
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* @pctl_offset: starting offset of the pin-bank registers.
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* @nr_pins: number of pins included in this bank.
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* @eint_base: base address of the pin-bank EINT registers.
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* @eint_func: function to set in CON register to configure pin as EINT.
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* @eint_type: type of the external interrupt supported by the bank.
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* @eint_mask: bit mask of pins which support EINT function.
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* @eint_offset: SoC-specific EINT register or interrupt offset of bank.
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* @name: name to be prefixed for each pin in this pin bank.
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* @pin_base: starting pin number of the bank.
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* @soc_priv: per-bank private data for SoC-specific code.
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* @of_node: OF node of the bank.
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* @drvdata: link to controller driver data
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* @irq_domain: IRQ domain of the bank.
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* @gpio_chip: GPIO chip of the bank.
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* @grange: linux gpio pin range supported by this bank.
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* @irq_chip: link to irq chip for external gpio and wakeup interrupts.
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* @slock: spinlock protecting bank registers
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* @pm_save: saved register values during suspend
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*/
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struct samsung_pin_bank {
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const struct samsung_pin_bank_type *type;
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void __iomem *pctl_base;
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u32 pctl_offset;
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u8 nr_pins;
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void __iomem *eint_base;
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u8 eint_func;
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enum eint_type eint_type;
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u32 eint_mask;
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u32 eint_offset;
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const char *name;
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u32 pin_base;
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void *soc_priv;
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struct device_node *of_node;
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struct samsung_pinctrl_drv_data *drvdata;
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struct irq_domain *irq_domain;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range grange;
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struct exynos_irq_chip *irq_chip;
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spinlock_t slock;
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u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
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};
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/**
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* struct samsung_retention_data: runtime pin-bank retention control data.
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* @regs: array of PMU registers to control pad retention.
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* @nr_regs: number of registers in @regs array.
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* @value: value to store to registers to turn off retention.
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* @refcnt: atomic counter if retention control affects more than one bank.
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* @priv: retention control code private data
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* @enable: platform specific callback to enter retention mode.
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* @disable: platform specific callback to exit retention mode.
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**/
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struct samsung_retention_ctrl {
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const u32 *regs;
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int nr_regs;
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u32 value;
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atomic_t *refcnt;
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void *priv;
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void (*enable)(struct samsung_pinctrl_drv_data *);
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void (*disable)(struct samsung_pinctrl_drv_data *);
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};
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/**
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* struct samsung_retention_data: represent a pin-bank retention control data.
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* @regs: array of PMU registers to control pad retention.
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* @nr_regs: number of registers in @regs array.
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* @value: value to store to registers to turn off retention.
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* @refcnt: atomic counter if retention control affects more than one bank.
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* @init: platform specific callback to initialize retention control.
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**/
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struct samsung_retention_data {
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const u32 *regs;
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int nr_regs;
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u32 value;
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atomic_t *refcnt;
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struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,
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const struct samsung_retention_data *);
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};
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/**
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* struct samsung_pin_ctrl: represent a pin controller.
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* @pin_banks: list of pin banks included in this controller.
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* @nr_banks: number of pin banks.
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* @nr_ext_resources: number of the extra base address for pin banks.
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* @retention_data: configuration data for retention control.
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* @eint_gpio_init: platform specific callback to setup the external gpio
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* interrupts for the controller.
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* @eint_wkup_init: platform specific callback to setup the external wakeup
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* interrupts for the controller.
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* @suspend: platform specific suspend callback, executed during pin controller
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* device suspend, see samsung_pinctrl_suspend()
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* @resume: platform specific resume callback, executed during pin controller
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* device suspend, see samsung_pinctrl_resume()
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*
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* External wakeup interrupts must define at least eint_wkup_init,
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* retention_data and suspend in order for proper suspend/resume to work.
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*/
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struct samsung_pin_ctrl {
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const struct samsung_pin_bank_data *pin_banks;
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unsigned int nr_banks;
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unsigned int nr_ext_resources;
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const struct samsung_retention_data *retention_data;
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int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
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int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
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void (*suspend)(struct samsung_pinctrl_drv_data *);
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void (*resume)(struct samsung_pinctrl_drv_data *);
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};
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/**
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* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
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* @node: global list node
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* @virt_base: register base address of the controller; this will be equal
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* to each bank samsung_pin_bank->pctl_base and used on legacy
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* platforms (like S3C24XX or S3C64XX) which has to access the base
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* through samsung_pinctrl_drv_data, not samsung_pin_bank).
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* @dev: device instance representing the controller.
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* @irq: interrpt number used by the controller to notify gpio interrupts.
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* @ctrl: pin controller instance managed by the driver.
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* @pctl: pin controller descriptor registered with the pinctrl subsystem.
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* @pctl_dev: cookie representing pinctrl device instance.
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* @pin_groups: list of pin groups available to the driver.
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* @nr_groups: number of such pin groups.
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* @pmx_functions: list of pin functions available to the driver.
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* @nr_function: number of such pin functions.
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* @pin_base: starting system wide pin number.
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* @nr_pins: number of pins supported by the controller.
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* @retention_ctrl: retention control runtime data.
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* @suspend: platform specific suspend callback, executed during pin controller
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* device suspend, see samsung_pinctrl_suspend()
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* @resume: platform specific resume callback, executed during pin controller
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* device suspend, see samsung_pinctrl_resume()
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*/
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struct samsung_pinctrl_drv_data {
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struct list_head node;
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void __iomem *virt_base;
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struct device *dev;
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int irq;
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struct pinctrl_desc pctl;
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struct pinctrl_dev *pctl_dev;
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const struct samsung_pin_group *pin_groups;
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unsigned int nr_groups;
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const struct samsung_pmx_func *pmx_functions;
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unsigned int nr_functions;
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struct samsung_pin_bank *pin_banks;
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unsigned int nr_banks;
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unsigned int pin_base;
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unsigned int nr_pins;
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struct samsung_retention_ctrl *retention_ctrl;
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void (*suspend)(struct samsung_pinctrl_drv_data *);
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void (*resume)(struct samsung_pinctrl_drv_data *);
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};
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/**
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* struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
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* @ctrl: array of pin controller data.
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* @num_ctrl: size of array @ctrl.
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*/
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struct samsung_pinctrl_of_match_data {
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const struct samsung_pin_ctrl *ctrl;
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unsigned int num_ctrl;
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};
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/**
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* struct samsung_pin_group: represent group of pins of a pinmux function.
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* @name: name of the pin group, used to lookup the group.
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* @pins: the pins included in this group.
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* @num_pins: number of pins included in this group.
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* @func: the function number to be programmed when selected.
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*/
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struct samsung_pin_group {
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const char *name;
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const unsigned int *pins;
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u8 num_pins;
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u8 func;
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};
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/**
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* struct samsung_pmx_func: represent a pin function.
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* @name: name of the pin function, used to lookup the function.
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* @groups: one or more names of pin groups that provide this function.
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* @num_groups: number of groups included in @groups.
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*/
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struct samsung_pmx_func {
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const char *name;
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const char **groups;
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u8 num_groups;
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u32 val;
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};
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/* list of all exported SoC specific data */
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extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5250_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
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extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;
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extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;
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extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
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#endif /* __PINCTRL_SAMSUNG_H */
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