529 lines
18 KiB
C
529 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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#ifndef _IAVF_ADMINQ_CMD_H_
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#define _IAVF_ADMINQ_CMD_H_
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/* This header file defines the iavf Admin Queue commands and is shared between
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* iavf Firmware and Software.
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*
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* This file needs to comply with the Linux Kernel coding style.
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*/
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#define IAVF_FW_API_VERSION_MAJOR 0x0001
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#define IAVF_FW_API_VERSION_MINOR_X722 0x0005
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#define IAVF_FW_API_VERSION_MINOR_X710 0x0008
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#define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \
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IAVF_FW_API_VERSION_MINOR_X710 : \
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IAVF_FW_API_VERSION_MINOR_X722)
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/* API version 1.7 implements additional link and PHY-specific APIs */
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#define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
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struct iavf_aq_desc {
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__le16 flags;
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__le16 opcode;
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__le16 datalen;
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__le16 retval;
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__le32 cookie_high;
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__le32 cookie_low;
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union {
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struct {
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__le32 param0;
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__le32 param1;
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__le32 param2;
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__le32 param3;
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} internal;
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struct {
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__le32 param0;
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__le32 param1;
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__le32 addr_high;
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__le32 addr_low;
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} external;
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u8 raw[16];
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} params;
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};
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/* Flags sub-structure
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* |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
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* |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
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*/
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/* command flags and offsets*/
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#define IAVF_AQ_FLAG_DD_SHIFT 0
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#define IAVF_AQ_FLAG_CMP_SHIFT 1
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#define IAVF_AQ_FLAG_ERR_SHIFT 2
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#define IAVF_AQ_FLAG_VFE_SHIFT 3
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#define IAVF_AQ_FLAG_LB_SHIFT 9
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#define IAVF_AQ_FLAG_RD_SHIFT 10
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#define IAVF_AQ_FLAG_VFC_SHIFT 11
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#define IAVF_AQ_FLAG_BUF_SHIFT 12
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#define IAVF_AQ_FLAG_SI_SHIFT 13
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#define IAVF_AQ_FLAG_EI_SHIFT 14
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#define IAVF_AQ_FLAG_FE_SHIFT 15
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#define IAVF_AQ_FLAG_DD BIT(IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
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#define IAVF_AQ_FLAG_CMP BIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
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#define IAVF_AQ_FLAG_ERR BIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
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#define IAVF_AQ_FLAG_VFE BIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8 */
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#define IAVF_AQ_FLAG_LB BIT(IAVF_AQ_FLAG_LB_SHIFT) /* 0x200 */
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#define IAVF_AQ_FLAG_RD BIT(IAVF_AQ_FLAG_RD_SHIFT) /* 0x400 */
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#define IAVF_AQ_FLAG_VFC BIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800 */
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#define IAVF_AQ_FLAG_BUF BIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
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#define IAVF_AQ_FLAG_SI BIT(IAVF_AQ_FLAG_SI_SHIFT) /* 0x2000 */
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#define IAVF_AQ_FLAG_EI BIT(IAVF_AQ_FLAG_EI_SHIFT) /* 0x4000 */
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#define IAVF_AQ_FLAG_FE BIT(IAVF_AQ_FLAG_FE_SHIFT) /* 0x8000 */
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/* error codes */
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enum iavf_admin_queue_err {
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IAVF_AQ_RC_OK = 0, /* success */
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IAVF_AQ_RC_EPERM = 1, /* Operation not permitted */
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IAVF_AQ_RC_ENOENT = 2, /* No such element */
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IAVF_AQ_RC_ESRCH = 3, /* Bad opcode */
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IAVF_AQ_RC_EINTR = 4, /* operation interrupted */
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IAVF_AQ_RC_EIO = 5, /* I/O error */
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IAVF_AQ_RC_ENXIO = 6, /* No such resource */
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IAVF_AQ_RC_E2BIG = 7, /* Arg too long */
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IAVF_AQ_RC_EAGAIN = 8, /* Try again */
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IAVF_AQ_RC_ENOMEM = 9, /* Out of memory */
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IAVF_AQ_RC_EACCES = 10, /* Permission denied */
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IAVF_AQ_RC_EFAULT = 11, /* Bad address */
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IAVF_AQ_RC_EBUSY = 12, /* Device or resource busy */
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IAVF_AQ_RC_EEXIST = 13, /* object already exists */
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IAVF_AQ_RC_EINVAL = 14, /* Invalid argument */
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IAVF_AQ_RC_ENOTTY = 15, /* Not a typewriter */
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IAVF_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
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IAVF_AQ_RC_ENOSYS = 17, /* Function not implemented */
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IAVF_AQ_RC_ERANGE = 18, /* Parameter out of range */
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IAVF_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
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IAVF_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
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IAVF_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
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IAVF_AQ_RC_EFBIG = 22, /* File too large */
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};
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/* Admin Queue command opcodes */
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enum iavf_admin_queue_opc {
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/* aq commands */
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iavf_aqc_opc_get_version = 0x0001,
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iavf_aqc_opc_driver_version = 0x0002,
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iavf_aqc_opc_queue_shutdown = 0x0003,
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iavf_aqc_opc_set_pf_context = 0x0004,
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/* resource ownership */
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iavf_aqc_opc_request_resource = 0x0008,
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iavf_aqc_opc_release_resource = 0x0009,
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iavf_aqc_opc_list_func_capabilities = 0x000A,
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iavf_aqc_opc_list_dev_capabilities = 0x000B,
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/* Proxy commands */
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iavf_aqc_opc_set_proxy_config = 0x0104,
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iavf_aqc_opc_set_ns_proxy_table_entry = 0x0105,
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/* LAA */
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iavf_aqc_opc_mac_address_read = 0x0107,
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iavf_aqc_opc_mac_address_write = 0x0108,
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/* PXE */
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iavf_aqc_opc_clear_pxe_mode = 0x0110,
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/* WoL commands */
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iavf_aqc_opc_set_wol_filter = 0x0120,
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iavf_aqc_opc_get_wake_reason = 0x0121,
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/* internal switch commands */
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iavf_aqc_opc_get_switch_config = 0x0200,
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iavf_aqc_opc_add_statistics = 0x0201,
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iavf_aqc_opc_remove_statistics = 0x0202,
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iavf_aqc_opc_set_port_parameters = 0x0203,
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iavf_aqc_opc_get_switch_resource_alloc = 0x0204,
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iavf_aqc_opc_set_switch_config = 0x0205,
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iavf_aqc_opc_rx_ctl_reg_read = 0x0206,
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iavf_aqc_opc_rx_ctl_reg_write = 0x0207,
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iavf_aqc_opc_add_vsi = 0x0210,
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iavf_aqc_opc_update_vsi_parameters = 0x0211,
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iavf_aqc_opc_get_vsi_parameters = 0x0212,
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iavf_aqc_opc_add_pv = 0x0220,
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iavf_aqc_opc_update_pv_parameters = 0x0221,
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iavf_aqc_opc_get_pv_parameters = 0x0222,
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iavf_aqc_opc_add_veb = 0x0230,
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iavf_aqc_opc_update_veb_parameters = 0x0231,
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iavf_aqc_opc_get_veb_parameters = 0x0232,
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iavf_aqc_opc_delete_element = 0x0243,
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iavf_aqc_opc_add_macvlan = 0x0250,
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iavf_aqc_opc_remove_macvlan = 0x0251,
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iavf_aqc_opc_add_vlan = 0x0252,
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iavf_aqc_opc_remove_vlan = 0x0253,
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iavf_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
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iavf_aqc_opc_add_tag = 0x0255,
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iavf_aqc_opc_remove_tag = 0x0256,
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iavf_aqc_opc_add_multicast_etag = 0x0257,
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iavf_aqc_opc_remove_multicast_etag = 0x0258,
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iavf_aqc_opc_update_tag = 0x0259,
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iavf_aqc_opc_add_control_packet_filter = 0x025A,
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iavf_aqc_opc_remove_control_packet_filter = 0x025B,
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iavf_aqc_opc_add_cloud_filters = 0x025C,
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iavf_aqc_opc_remove_cloud_filters = 0x025D,
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iavf_aqc_opc_clear_wol_switch_filters = 0x025E,
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iavf_aqc_opc_add_mirror_rule = 0x0260,
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iavf_aqc_opc_delete_mirror_rule = 0x0261,
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/* Dynamic Device Personalization */
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iavf_aqc_opc_write_personalization_profile = 0x0270,
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iavf_aqc_opc_get_personalization_profile_list = 0x0271,
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/* DCB commands */
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iavf_aqc_opc_dcb_ignore_pfc = 0x0301,
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iavf_aqc_opc_dcb_updated = 0x0302,
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iavf_aqc_opc_set_dcb_parameters = 0x0303,
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/* TX scheduler */
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iavf_aqc_opc_configure_vsi_bw_limit = 0x0400,
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iavf_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
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iavf_aqc_opc_configure_vsi_tc_bw = 0x0407,
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iavf_aqc_opc_query_vsi_bw_config = 0x0408,
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iavf_aqc_opc_query_vsi_ets_sla_config = 0x040A,
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iavf_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
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iavf_aqc_opc_enable_switching_comp_ets = 0x0413,
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iavf_aqc_opc_modify_switching_comp_ets = 0x0414,
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iavf_aqc_opc_disable_switching_comp_ets = 0x0415,
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iavf_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
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iavf_aqc_opc_configure_switching_comp_bw_config = 0x0417,
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iavf_aqc_opc_query_switching_comp_ets_config = 0x0418,
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iavf_aqc_opc_query_port_ets_config = 0x0419,
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iavf_aqc_opc_query_switching_comp_bw_config = 0x041A,
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iavf_aqc_opc_suspend_port_tx = 0x041B,
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iavf_aqc_opc_resume_port_tx = 0x041C,
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iavf_aqc_opc_configure_partition_bw = 0x041D,
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/* hmc */
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iavf_aqc_opc_query_hmc_resource_profile = 0x0500,
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iavf_aqc_opc_set_hmc_resource_profile = 0x0501,
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/* phy commands*/
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iavf_aqc_opc_get_phy_abilities = 0x0600,
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iavf_aqc_opc_set_phy_config = 0x0601,
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iavf_aqc_opc_set_mac_config = 0x0603,
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iavf_aqc_opc_set_link_restart_an = 0x0605,
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iavf_aqc_opc_get_link_status = 0x0607,
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iavf_aqc_opc_set_phy_int_mask = 0x0613,
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iavf_aqc_opc_get_local_advt_reg = 0x0614,
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iavf_aqc_opc_set_local_advt_reg = 0x0615,
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iavf_aqc_opc_get_partner_advt = 0x0616,
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iavf_aqc_opc_set_lb_modes = 0x0618,
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iavf_aqc_opc_get_phy_wol_caps = 0x0621,
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iavf_aqc_opc_set_phy_debug = 0x0622,
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iavf_aqc_opc_upload_ext_phy_fm = 0x0625,
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iavf_aqc_opc_run_phy_activity = 0x0626,
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iavf_aqc_opc_set_phy_register = 0x0628,
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iavf_aqc_opc_get_phy_register = 0x0629,
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/* NVM commands */
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iavf_aqc_opc_nvm_read = 0x0701,
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iavf_aqc_opc_nvm_erase = 0x0702,
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iavf_aqc_opc_nvm_update = 0x0703,
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iavf_aqc_opc_nvm_config_read = 0x0704,
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iavf_aqc_opc_nvm_config_write = 0x0705,
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iavf_aqc_opc_oem_post_update = 0x0720,
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iavf_aqc_opc_thermal_sensor = 0x0721,
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/* virtualization commands */
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iavf_aqc_opc_send_msg_to_pf = 0x0801,
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iavf_aqc_opc_send_msg_to_vf = 0x0802,
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iavf_aqc_opc_send_msg_to_peer = 0x0803,
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/* alternate structure */
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iavf_aqc_opc_alternate_write = 0x0900,
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iavf_aqc_opc_alternate_write_indirect = 0x0901,
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iavf_aqc_opc_alternate_read = 0x0902,
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iavf_aqc_opc_alternate_read_indirect = 0x0903,
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iavf_aqc_opc_alternate_write_done = 0x0904,
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iavf_aqc_opc_alternate_set_mode = 0x0905,
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iavf_aqc_opc_alternate_clear_port = 0x0906,
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/* LLDP commands */
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iavf_aqc_opc_lldp_get_mib = 0x0A00,
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iavf_aqc_opc_lldp_update_mib = 0x0A01,
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iavf_aqc_opc_lldp_add_tlv = 0x0A02,
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iavf_aqc_opc_lldp_update_tlv = 0x0A03,
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iavf_aqc_opc_lldp_delete_tlv = 0x0A04,
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iavf_aqc_opc_lldp_stop = 0x0A05,
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iavf_aqc_opc_lldp_start = 0x0A06,
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/* Tunnel commands */
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iavf_aqc_opc_add_udp_tunnel = 0x0B00,
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iavf_aqc_opc_del_udp_tunnel = 0x0B01,
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iavf_aqc_opc_set_rss_key = 0x0B02,
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iavf_aqc_opc_set_rss_lut = 0x0B03,
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iavf_aqc_opc_get_rss_key = 0x0B04,
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iavf_aqc_opc_get_rss_lut = 0x0B05,
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/* Async Events */
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iavf_aqc_opc_event_lan_overflow = 0x1001,
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/* OEM commands */
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iavf_aqc_opc_oem_parameter_change = 0xFE00,
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iavf_aqc_opc_oem_device_status_change = 0xFE01,
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iavf_aqc_opc_oem_ocsd_initialize = 0xFE02,
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iavf_aqc_opc_oem_ocbb_initialize = 0xFE03,
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/* debug commands */
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iavf_aqc_opc_debug_read_reg = 0xFF03,
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iavf_aqc_opc_debug_write_reg = 0xFF04,
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iavf_aqc_opc_debug_modify_reg = 0xFF07,
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iavf_aqc_opc_debug_dump_internals = 0xFF08,
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};
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/* command structures and indirect data structures */
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/* Structure naming conventions:
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* - no suffix for direct command descriptor structures
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* - _data for indirect sent data
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* - _resp for indirect return data (data which is both will use _data)
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* - _completion for direct return data
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* - _element_ for repeated elements (may also be _data or _resp)
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*
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* Command structures are expected to overlay the params.raw member of the basic
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* descriptor, and as such cannot exceed 16 bytes in length.
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*/
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/* This macro is used to generate a compilation error if a structure
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* is not exactly the correct length. It gives a divide by zero error if the
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* structure is not of the correct size, otherwise it creates an enum that is
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* never used.
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*/
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#define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \
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{ iavf_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }
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/* This macro is used extensively to ensure that command structures are 16
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* bytes in length as they have to map to the raw array of that size.
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*/
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#define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X)
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/* Queue Shutdown (direct 0x0003) */
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struct iavf_aqc_queue_shutdown {
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__le32 driver_unloading;
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#define IAVF_AQ_DRIVER_UNLOADING 0x1
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u8 reserved[12];
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};
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IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
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struct iavf_aqc_vsi_properties_data {
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/* first 96 byte are written by SW */
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__le16 valid_sections;
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#define IAVF_AQ_VSI_PROP_SWITCH_VALID 0x0001
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#define IAVF_AQ_VSI_PROP_SECURITY_VALID 0x0002
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#define IAVF_AQ_VSI_PROP_VLAN_VALID 0x0004
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#define IAVF_AQ_VSI_PROP_CAS_PV_VALID 0x0008
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#define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
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#define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
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#define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
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#define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
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#define IAVF_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
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#define IAVF_AQ_VSI_PROP_SCHED_VALID 0x0200
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/* switch section */
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__le16 switch_id; /* 12bit id combined with flags below */
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#define IAVF_AQ_VSI_SW_ID_SHIFT 0x0000
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#define IAVF_AQ_VSI_SW_ID_MASK (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT)
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#define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
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#define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
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#define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
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u8 sw_reserved[2];
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/* security section */
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u8 sec_flags;
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#define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
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#define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
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#define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
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u8 sec_reserved;
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/* VLAN section */
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__le16 pvid; /* VLANS include priority bits */
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__le16 fcoe_pvid;
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u8 port_vlan_flags;
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#define IAVF_AQ_VSI_PVLAN_MODE_SHIFT 0x00
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#define IAVF_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
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IAVF_AQ_VSI_PVLAN_MODE_SHIFT)
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#define IAVF_AQ_VSI_PVLAN_MODE_TAGGED 0x01
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#define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
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#define IAVF_AQ_VSI_PVLAN_MODE_ALL 0x03
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#define IAVF_AQ_VSI_PVLAN_INSERT_PVID 0x04
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#define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
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#define IAVF_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
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IAVF_AQ_VSI_PVLAN_EMOD_SHIFT)
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#define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
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#define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
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#define IAVF_AQ_VSI_PVLAN_EMOD_STR 0x10
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#define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
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u8 pvlan_reserved[3];
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/* ingress egress up sections */
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__le32 ingress_table; /* bitmap, 3 bits per up */
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#define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT 0
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#define IAVF_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT 3
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#define IAVF_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT 6
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#define IAVF_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT 9
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#define IAVF_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT 12
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#define IAVF_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT 15
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#define IAVF_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT 18
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#define IAVF_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT)
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#define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT 21
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#define IAVF_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
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IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT)
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__le32 egress_table; /* same defines as for ingress table */
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/* cascaded PV section */
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__le16 cas_pv_tag;
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u8 cas_pv_flags;
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#define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
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#define IAVF_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
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IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT)
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#define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
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#define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
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#define IAVF_AQ_VSI_CAS_PV_TAGX_COPY 0x02
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#define IAVF_AQ_VSI_CAS_PV_INSERT_TAG 0x10
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#define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
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#define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
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u8 cas_pv_reserved;
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/* queue mapping section */
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__le16 mapping_flags;
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#define IAVF_AQ_VSI_QUE_MAP_CONTIG 0x0
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#define IAVF_AQ_VSI_QUE_MAP_NONCONTIG 0x1
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__le16 queue_mapping[16];
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#define IAVF_AQ_VSI_QUEUE_SHIFT 0x0
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#define IAVF_AQ_VSI_QUEUE_MASK (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT)
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__le16 tc_mapping[8];
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#define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
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#define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
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IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT)
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#define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
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#define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
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IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT)
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/* queueing option section */
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u8 queueing_opt_flags;
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#define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
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#define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
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#define IAVF_AQ_VSI_QUE_OPT_TCP_ENA 0x10
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#define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
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#define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
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#define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
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u8 queueing_opt_reserved[3];
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/* scheduler section */
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u8 up_enable_bits;
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u8 sched_reserved;
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/* outer up section */
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__le32 outer_up_table; /* same structure and defines as ingress tbl */
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u8 cmd_reserved[8];
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/* last 32 bytes are written by FW */
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__le16 qs_handle[8];
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#define IAVF_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
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__le16 stat_counter_idx;
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__le16 sched_id;
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u8 resp_reserved[12];
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};
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IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
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/* Get VEB Parameters (direct 0x0232)
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* uses iavf_aqc_switch_seid for the descriptor
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*/
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struct iavf_aqc_get_veb_parameters_completion {
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__le16 seid;
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__le16 switch_id;
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__le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
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__le16 statistic_index;
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|
__le16 vebs_used;
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|
__le16 vebs_free;
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u8 reserved[4];
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};
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IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
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#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
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#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
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#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
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#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
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#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
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#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
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enum iavf_aq_link_speed {
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IAVF_LINK_SPEED_UNKNOWN = 0,
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IAVF_LINK_SPEED_100MB = BIT(IAVF_LINK_SPEED_100MB_SHIFT),
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IAVF_LINK_SPEED_1GB = BIT(IAVF_LINK_SPEED_1000MB_SHIFT),
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IAVF_LINK_SPEED_10GB = BIT(IAVF_LINK_SPEED_10GB_SHIFT),
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IAVF_LINK_SPEED_40GB = BIT(IAVF_LINK_SPEED_40GB_SHIFT),
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IAVF_LINK_SPEED_20GB = BIT(IAVF_LINK_SPEED_20GB_SHIFT),
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IAVF_LINK_SPEED_25GB = BIT(IAVF_LINK_SPEED_25GB_SHIFT),
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};
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/* Send to PF command (indirect 0x0801) id is only used by PF
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* Send to VF command (indirect 0x0802) id is only used by PF
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* Send to Peer PF command (indirect 0x0803)
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*/
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struct iavf_aqc_pf_vf_message {
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|
__le32 id;
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|
u8 reserved[4];
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__le32 addr_high;
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__le32 addr_low;
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};
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IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
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struct iavf_aqc_get_set_rss_key {
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#define IAVF_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
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#define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
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#define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
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IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
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__le16 vsi_id;
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u8 reserved[6];
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__le32 addr_high;
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__le32 addr_low;
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};
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IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key);
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struct iavf_aqc_get_set_rss_key_data {
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u8 standard_rss_key[0x28];
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u8 extended_hash_key[0xc];
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};
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IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data);
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struct iavf_aqc_get_set_rss_lut {
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|
#define IAVF_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
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#define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
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|
#define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
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IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
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|
__le16 vsi_id;
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|
#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
|
|
#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
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|
BIT(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
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|
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|
#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
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|
#define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
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|
__le16 flags;
|
|
u8 reserved[4];
|
|
__le32 addr_high;
|
|
__le32 addr_low;
|
|
};
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|
|
|
IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
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#endif /* _IAVF_ADMINQ_CMD_H_ */
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