158 lines
3.6 KiB
C
158 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright (c) 2016-2017 Hisilicon Limited.
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#ifndef __HCLGE_TM_H
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#define __HCLGE_TM_H
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#include <linux/types.h>
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/* MAC Pause */
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#define HCLGE_TX_MAC_PAUSE_EN_MSK BIT(0)
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#define HCLGE_RX_MAC_PAUSE_EN_MSK BIT(1)
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#define HCLGE_TM_PORT_BASE_MODE_MSK BIT(0)
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#define HCLGE_DEFAULT_PAUSE_TRANS_GAP 0x7F
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#define HCLGE_DEFAULT_PAUSE_TRANS_TIME 0xFFFF
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/* SP or DWRR */
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#define HCLGE_TM_TX_SCHD_DWRR_MSK BIT(0)
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#define HCLGE_TM_TX_SCHD_SP_MSK (0xFE)
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struct hclge_pg_to_pri_link_cmd {
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u8 pg_id;
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u8 rsvd1[3];
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u8 pri_bit_map;
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};
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struct hclge_qs_to_pri_link_cmd {
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__le16 qs_id;
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__le16 rsvd;
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u8 priority;
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#define HCLGE_TM_QS_PRI_LINK_VLD_MSK BIT(0)
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u8 link_vld;
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};
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struct hclge_nq_to_qs_link_cmd {
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__le16 nq_id;
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__le16 rsvd;
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#define HCLGE_TM_Q_QS_LINK_VLD_MSK BIT(10)
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__le16 qset_id;
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};
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struct hclge_tqp_tx_queue_tc_cmd {
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__le16 queue_id;
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__le16 rsvd;
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u8 tc_id;
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u8 rev[3];
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};
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struct hclge_pg_weight_cmd {
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u8 pg_id;
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u8 dwrr;
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};
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struct hclge_priority_weight_cmd {
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u8 pri_id;
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u8 dwrr;
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};
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struct hclge_qs_weight_cmd {
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__le16 qs_id;
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u8 dwrr;
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};
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struct hclge_ets_tc_weight_cmd {
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u8 tc_weight[HNAE3_MAX_TC];
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u8 weight_offset;
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u8 rsvd[15];
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};
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#define HCLGE_TM_SHAP_IR_B_MSK GENMASK(7, 0)
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#define HCLGE_TM_SHAP_IR_B_LSH 0
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#define HCLGE_TM_SHAP_IR_U_MSK GENMASK(11, 8)
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#define HCLGE_TM_SHAP_IR_U_LSH 8
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#define HCLGE_TM_SHAP_IR_S_MSK GENMASK(15, 12)
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#define HCLGE_TM_SHAP_IR_S_LSH 12
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#define HCLGE_TM_SHAP_BS_B_MSK GENMASK(20, 16)
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#define HCLGE_TM_SHAP_BS_B_LSH 16
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#define HCLGE_TM_SHAP_BS_S_MSK GENMASK(25, 21)
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#define HCLGE_TM_SHAP_BS_S_LSH 21
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enum hclge_shap_bucket {
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HCLGE_TM_SHAP_C_BUCKET = 0,
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HCLGE_TM_SHAP_P_BUCKET,
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};
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struct hclge_pri_shapping_cmd {
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u8 pri_id;
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u8 rsvd[3];
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__le32 pri_shapping_para;
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};
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struct hclge_pg_shapping_cmd {
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u8 pg_id;
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u8 rsvd[3];
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__le32 pg_shapping_para;
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};
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#define HCLGE_BP_GRP_NUM 32
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#define HCLGE_BP_SUB_GRP_ID_S 0
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#define HCLGE_BP_SUB_GRP_ID_M GENMASK(4, 0)
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#define HCLGE_BP_GRP_ID_S 5
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#define HCLGE_BP_GRP_ID_M GENMASK(9, 5)
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struct hclge_bp_to_qs_map_cmd {
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u8 tc_id;
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u8 rsvd[2];
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u8 qs_group_id;
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__le32 qs_bit_map;
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u32 rsvd1;
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};
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struct hclge_pfc_en_cmd {
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u8 tx_rx_en_bitmap;
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u8 pri_en_bitmap;
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};
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struct hclge_cfg_pause_param_cmd {
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u8 mac_addr[ETH_ALEN];
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u8 pause_trans_gap;
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u8 rsvd;
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__le16 pause_trans_time;
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u8 rsvd1[6];
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/* extra mac address to do double check for pause frame */
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u8 mac_addr_extra[ETH_ALEN];
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u16 rsvd2;
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};
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struct hclge_pfc_stats_cmd {
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__le64 pkt_num[3];
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};
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struct hclge_port_shapping_cmd {
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__le32 port_shapping_para;
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};
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#define hclge_tm_set_field(dest, string, val) \
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hnae3_set_field((dest), \
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(HCLGE_TM_SHAP_##string##_MSK), \
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(HCLGE_TM_SHAP_##string##_LSH), val)
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#define hclge_tm_get_field(src, string) \
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hnae3_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \
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(HCLGE_TM_SHAP_##string##_LSH))
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int hclge_tm_schd_init(struct hclge_dev *hdev);
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int hclge_tm_vport_map_update(struct hclge_dev *hdev);
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int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init);
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int hclge_tm_schd_setup_hw(struct hclge_dev *hdev);
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void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);
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void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);
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void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
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int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
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int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
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int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
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int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
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int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
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int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
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#endif
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