600 lines
16 KiB
C
600 lines
16 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Google virtual Ethernet (gve) driver
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*
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* Copyright (C) 2015-2019 Google, Inc.
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*/
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#include "gve.h"
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#include "gve_adminq.h"
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#include <linux/ip.h>
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#include <linux/tcp.h>
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#include <linux/vmalloc.h>
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#include <linux/skbuff.h>
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static inline void gve_tx_put_doorbell(struct gve_priv *priv,
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struct gve_queue_resources *q_resources,
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u32 val)
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{
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iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]);
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}
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/* gvnic can only transmit from a Registered Segment.
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* We copy skb payloads into the registered segment before writing Tx
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* descriptors and ringing the Tx doorbell.
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*
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* gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
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* free allocations in the order they were allocated.
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*/
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static int gve_tx_fifo_init(struct gve_priv *priv, struct gve_tx_fifo *fifo)
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{
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fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP,
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PAGE_KERNEL);
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if (unlikely(!fifo->base)) {
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netif_err(priv, drv, priv->dev, "Failed to vmap fifo, qpl_id = %d\n",
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fifo->qpl->id);
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return -ENOMEM;
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}
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fifo->size = fifo->qpl->num_entries * PAGE_SIZE;
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atomic_set(&fifo->available, fifo->size);
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fifo->head = 0;
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return 0;
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}
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static void gve_tx_fifo_release(struct gve_priv *priv, struct gve_tx_fifo *fifo)
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{
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WARN(atomic_read(&fifo->available) != fifo->size,
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"Releasing non-empty fifo");
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vunmap(fifo->base);
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}
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static int gve_tx_fifo_pad_alloc_one_frag(struct gve_tx_fifo *fifo,
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size_t bytes)
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{
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return (fifo->head + bytes < fifo->size) ? 0 : fifo->size - fifo->head;
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}
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static bool gve_tx_fifo_can_alloc(struct gve_tx_fifo *fifo, size_t bytes)
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{
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return (atomic_read(&fifo->available) <= bytes) ? false : true;
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}
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/* gve_tx_alloc_fifo - Allocate fragment(s) from Tx FIFO
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* @fifo: FIFO to allocate from
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* @bytes: Allocation size
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* @iov: Scatter-gather elements to fill with allocation fragment base/len
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*
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* Returns number of valid elements in iov[] or negative on error.
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*
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* Allocations from a given FIFO must be externally synchronized but concurrent
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* allocation and frees are allowed.
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*/
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static int gve_tx_alloc_fifo(struct gve_tx_fifo *fifo, size_t bytes,
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struct gve_tx_iovec iov[2])
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{
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size_t overflow, padding;
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u32 aligned_head;
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int nfrags = 0;
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if (!bytes)
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return 0;
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/* This check happens before we know how much padding is needed to
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* align to a cacheline boundary for the payload, but that is fine,
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* because the FIFO head always start aligned, and the FIFO's boundaries
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* are aligned, so if there is space for the data, there is space for
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* the padding to the next alignment.
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*/
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WARN(!gve_tx_fifo_can_alloc(fifo, bytes),
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"Reached %s when there's not enough space in the fifo", __func__);
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nfrags++;
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iov[0].iov_offset = fifo->head;
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iov[0].iov_len = bytes;
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fifo->head += bytes;
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if (fifo->head > fifo->size) {
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/* If the allocation did not fit in the tail fragment of the
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* FIFO, also use the head fragment.
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*/
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nfrags++;
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overflow = fifo->head - fifo->size;
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iov[0].iov_len -= overflow;
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iov[1].iov_offset = 0; /* Start of fifo*/
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iov[1].iov_len = overflow;
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fifo->head = overflow;
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}
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/* Re-align to a cacheline boundary */
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aligned_head = L1_CACHE_ALIGN(fifo->head);
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padding = aligned_head - fifo->head;
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iov[nfrags - 1].iov_padding = padding;
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atomic_sub(bytes + padding, &fifo->available);
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fifo->head = aligned_head;
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if (fifo->head == fifo->size)
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fifo->head = 0;
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return nfrags;
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}
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/* gve_tx_free_fifo - Return space to Tx FIFO
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* @fifo: FIFO to return fragments to
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* @bytes: Bytes to free
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*/
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static void gve_tx_free_fifo(struct gve_tx_fifo *fifo, size_t bytes)
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{
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atomic_add(bytes, &fifo->available);
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}
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static void gve_tx_remove_from_block(struct gve_priv *priv, int queue_idx)
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{
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struct gve_notify_block *block =
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&priv->ntfy_blocks[gve_tx_idx_to_ntfy(priv, queue_idx)];
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block->tx = NULL;
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}
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static int gve_clean_tx_done(struct gve_priv *priv, struct gve_tx_ring *tx,
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u32 to_do, bool try_to_wake);
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static void gve_tx_free_ring(struct gve_priv *priv, int idx)
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{
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struct gve_tx_ring *tx = &priv->tx[idx];
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struct device *hdev = &priv->pdev->dev;
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size_t bytes;
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u32 slots;
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gve_tx_remove_from_block(priv, idx);
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slots = tx->mask + 1;
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gve_clean_tx_done(priv, tx, tx->req, false);
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netdev_tx_reset_queue(tx->netdev_txq);
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dma_free_coherent(hdev, sizeof(*tx->q_resources),
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tx->q_resources, tx->q_resources_bus);
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tx->q_resources = NULL;
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gve_tx_fifo_release(priv, &tx->tx_fifo);
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gve_unassign_qpl(priv, tx->tx_fifo.qpl->id);
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tx->tx_fifo.qpl = NULL;
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bytes = sizeof(*tx->desc) * slots;
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dma_free_coherent(hdev, bytes, tx->desc, tx->bus);
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tx->desc = NULL;
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vfree(tx->info);
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tx->info = NULL;
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netif_dbg(priv, drv, priv->dev, "freed tx queue %d\n", idx);
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}
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static void gve_tx_add_to_block(struct gve_priv *priv, int queue_idx)
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{
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int ntfy_idx = gve_tx_idx_to_ntfy(priv, queue_idx);
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struct gve_notify_block *block = &priv->ntfy_blocks[ntfy_idx];
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struct gve_tx_ring *tx = &priv->tx[queue_idx];
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block->tx = tx;
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tx->ntfy_id = ntfy_idx;
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}
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static int gve_tx_alloc_ring(struct gve_priv *priv, int idx)
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{
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struct gve_tx_ring *tx = &priv->tx[idx];
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struct device *hdev = &priv->pdev->dev;
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u32 slots = priv->tx_desc_cnt;
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size_t bytes;
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/* Make sure everything is zeroed to start */
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memset(tx, 0, sizeof(*tx));
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tx->q_num = idx;
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tx->mask = slots - 1;
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/* alloc metadata */
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tx->info = vzalloc(sizeof(*tx->info) * slots);
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if (!tx->info)
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return -ENOMEM;
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/* alloc tx queue */
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bytes = sizeof(*tx->desc) * slots;
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tx->desc = dma_alloc_coherent(hdev, bytes, &tx->bus, GFP_KERNEL);
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if (!tx->desc)
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goto abort_with_info;
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tx->tx_fifo.qpl = gve_assign_tx_qpl(priv);
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/* map Tx FIFO */
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if (gve_tx_fifo_init(priv, &tx->tx_fifo))
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goto abort_with_desc;
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tx->q_resources =
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dma_alloc_coherent(hdev,
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sizeof(*tx->q_resources),
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&tx->q_resources_bus,
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GFP_KERNEL);
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if (!tx->q_resources)
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goto abort_with_fifo;
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netif_dbg(priv, drv, priv->dev, "tx[%d]->bus=%lx\n", idx,
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(unsigned long)tx->bus);
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tx->netdev_txq = netdev_get_tx_queue(priv->dev, idx);
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gve_tx_add_to_block(priv, idx);
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return 0;
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abort_with_fifo:
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gve_tx_fifo_release(priv, &tx->tx_fifo);
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abort_with_desc:
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dma_free_coherent(hdev, bytes, tx->desc, tx->bus);
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tx->desc = NULL;
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abort_with_info:
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vfree(tx->info);
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tx->info = NULL;
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return -ENOMEM;
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}
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int gve_tx_alloc_rings(struct gve_priv *priv)
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{
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int err = 0;
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int i;
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for (i = 0; i < priv->tx_cfg.num_queues; i++) {
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err = gve_tx_alloc_ring(priv, i);
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if (err) {
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netif_err(priv, drv, priv->dev,
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"Failed to alloc tx ring=%d: err=%d\n",
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i, err);
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break;
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}
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}
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/* Unallocate if there was an error */
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if (err) {
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int j;
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for (j = 0; j < i; j++)
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gve_tx_free_ring(priv, j);
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}
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return err;
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}
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void gve_tx_free_rings(struct gve_priv *priv)
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{
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int i;
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for (i = 0; i < priv->tx_cfg.num_queues; i++)
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gve_tx_free_ring(priv, i);
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}
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/* gve_tx_avail - Calculates the number of slots available in the ring
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* @tx: tx ring to check
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*
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* Returns the number of slots available
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*
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* The capacity of the queue is mask + 1. We don't need to reserve an entry.
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**/
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static inline u32 gve_tx_avail(struct gve_tx_ring *tx)
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{
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return tx->mask + 1 - (tx->req - tx->done);
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}
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static inline int gve_skb_fifo_bytes_required(struct gve_tx_ring *tx,
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struct sk_buff *skb)
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{
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int pad_bytes, align_hdr_pad;
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int bytes;
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int hlen;
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hlen = skb_is_gso(skb) ? skb_checksum_start_offset(skb) +
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tcp_hdrlen(skb) : skb_headlen(skb);
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pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo,
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hlen);
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/* We need to take into account the header alignment padding. */
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align_hdr_pad = L1_CACHE_ALIGN(hlen) - hlen;
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bytes = align_hdr_pad + pad_bytes + skb->len;
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return bytes;
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}
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/* The most descriptors we could need are 3 - 1 for the headers, 1 for
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* the beginning of the payload at the end of the FIFO, and 1 if the
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* payload wraps to the beginning of the FIFO.
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*/
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#define MAX_TX_DESC_NEEDED 3
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/* Check if sufficient resources (descriptor ring space, FIFO space) are
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* available to transmit the given number of bytes.
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*/
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static inline bool gve_can_tx(struct gve_tx_ring *tx, int bytes_required)
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{
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return (gve_tx_avail(tx) >= MAX_TX_DESC_NEEDED &&
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gve_tx_fifo_can_alloc(&tx->tx_fifo, bytes_required));
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}
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/* Stops the queue if the skb cannot be transmitted. */
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static int gve_maybe_stop_tx(struct gve_tx_ring *tx, struct sk_buff *skb)
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{
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int bytes_required;
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bytes_required = gve_skb_fifo_bytes_required(tx, skb);
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if (likely(gve_can_tx(tx, bytes_required)))
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return 0;
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/* No space, so stop the queue */
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tx->stop_queue++;
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netif_tx_stop_queue(tx->netdev_txq);
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smp_mb(); /* sync with restarting queue in gve_clean_tx_done() */
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/* Now check for resources again, in case gve_clean_tx_done() freed
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* resources after we checked and we stopped the queue after
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* gve_clean_tx_done() checked.
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*
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* gve_maybe_stop_tx() gve_clean_tx_done()
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* nsegs/can_alloc test failed
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* gve_tx_free_fifo()
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* if (tx queue stopped)
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* netif_tx_queue_wake()
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* netif_tx_stop_queue()
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* Need to check again for space here!
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*/
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if (likely(!gve_can_tx(tx, bytes_required)))
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return -EBUSY;
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netif_tx_start_queue(tx->netdev_txq);
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tx->wake_queue++;
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return 0;
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}
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static void gve_tx_fill_pkt_desc(union gve_tx_desc *pkt_desc,
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struct sk_buff *skb, bool is_gso,
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int l4_hdr_offset, u32 desc_cnt,
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u16 hlen, u64 addr)
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{
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/* l4_hdr_offset and csum_offset are in units of 16-bit words */
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if (is_gso) {
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pkt_desc->pkt.type_flags = GVE_TXD_TSO | GVE_TXF_L4CSUM;
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pkt_desc->pkt.l4_csum_offset = skb->csum_offset >> 1;
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pkt_desc->pkt.l4_hdr_offset = l4_hdr_offset >> 1;
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} else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
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pkt_desc->pkt.type_flags = GVE_TXD_STD | GVE_TXF_L4CSUM;
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pkt_desc->pkt.l4_csum_offset = skb->csum_offset >> 1;
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pkt_desc->pkt.l4_hdr_offset = l4_hdr_offset >> 1;
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} else {
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pkt_desc->pkt.type_flags = GVE_TXD_STD;
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pkt_desc->pkt.l4_csum_offset = 0;
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pkt_desc->pkt.l4_hdr_offset = 0;
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}
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pkt_desc->pkt.desc_cnt = desc_cnt;
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pkt_desc->pkt.len = cpu_to_be16(skb->len);
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pkt_desc->pkt.seg_len = cpu_to_be16(hlen);
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pkt_desc->pkt.seg_addr = cpu_to_be64(addr);
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}
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static void gve_tx_fill_seg_desc(union gve_tx_desc *seg_desc,
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struct sk_buff *skb, bool is_gso,
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u16 len, u64 addr)
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{
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seg_desc->seg.type_flags = GVE_TXD_SEG;
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if (is_gso) {
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if (skb_is_gso_v6(skb))
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seg_desc->seg.type_flags |= GVE_TXSF_IPV6;
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seg_desc->seg.l3_offset = skb_network_offset(skb) >> 1;
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seg_desc->seg.mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
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}
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seg_desc->seg.seg_len = cpu_to_be16(len);
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seg_desc->seg.seg_addr = cpu_to_be64(addr);
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}
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static void gve_dma_sync_for_device(struct device *dev, dma_addr_t *page_buses,
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u64 iov_offset, u64 iov_len)
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{
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u64 last_page = (iov_offset + iov_len - 1) / PAGE_SIZE;
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u64 first_page = iov_offset / PAGE_SIZE;
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dma_addr_t dma;
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u64 page;
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for (page = first_page; page <= last_page; page++) {
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dma = page_buses[page];
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dma_sync_single_for_device(dev, dma, PAGE_SIZE, DMA_TO_DEVICE);
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}
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}
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static int gve_tx_add_skb(struct gve_tx_ring *tx, struct sk_buff *skb,
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struct device *dev)
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{
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int pad_bytes, hlen, hdr_nfrags, payload_nfrags, l4_hdr_offset;
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union gve_tx_desc *pkt_desc, *seg_desc;
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struct gve_tx_buffer_state *info;
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bool is_gso = skb_is_gso(skb);
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u32 idx = tx->req & tx->mask;
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int payload_iov = 2;
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int copy_offset;
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u32 next_idx;
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int i;
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info = &tx->info[idx];
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pkt_desc = &tx->desc[idx];
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l4_hdr_offset = skb_checksum_start_offset(skb);
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/* If the skb is gso, then we want the tcp header in the first segment
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* otherwise we want the linear portion of the skb (which will contain
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* the checksum because skb->csum_start and skb->csum_offset are given
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* relative to skb->head) in the first segment.
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*/
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hlen = is_gso ? l4_hdr_offset + tcp_hdrlen(skb) :
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skb_headlen(skb);
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info->skb = skb;
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/* We don't want to split the header, so if necessary, pad to the end
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* of the fifo and then put the header at the beginning of the fifo.
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*/
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pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, hlen);
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hdr_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, hlen + pad_bytes,
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&info->iov[0]);
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WARN(!hdr_nfrags, "hdr_nfrags should never be 0!");
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payload_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, skb->len - hlen,
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&info->iov[payload_iov]);
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gve_tx_fill_pkt_desc(pkt_desc, skb, is_gso, l4_hdr_offset,
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1 + payload_nfrags, hlen,
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info->iov[hdr_nfrags - 1].iov_offset);
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skb_copy_bits(skb, 0,
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tx->tx_fifo.base + info->iov[hdr_nfrags - 1].iov_offset,
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hlen);
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gve_dma_sync_for_device(dev, tx->tx_fifo.qpl->page_buses,
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info->iov[hdr_nfrags - 1].iov_offset,
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info->iov[hdr_nfrags - 1].iov_len);
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copy_offset = hlen;
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for (i = payload_iov; i < payload_nfrags + payload_iov; i++) {
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next_idx = (tx->req + 1 + i - payload_iov) & tx->mask;
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seg_desc = &tx->desc[next_idx];
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gve_tx_fill_seg_desc(seg_desc, skb, is_gso,
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info->iov[i].iov_len,
|
|
info->iov[i].iov_offset);
|
|
|
|
skb_copy_bits(skb, copy_offset,
|
|
tx->tx_fifo.base + info->iov[i].iov_offset,
|
|
info->iov[i].iov_len);
|
|
gve_dma_sync_for_device(dev, tx->tx_fifo.qpl->page_buses,
|
|
info->iov[i].iov_offset,
|
|
info->iov[i].iov_len);
|
|
copy_offset += info->iov[i].iov_len;
|
|
}
|
|
|
|
return 1 + payload_nfrags;
|
|
}
|
|
|
|
netdev_tx_t gve_tx(struct sk_buff *skb, struct net_device *dev)
|
|
{
|
|
struct gve_priv *priv = netdev_priv(dev);
|
|
struct gve_tx_ring *tx;
|
|
int nsegs;
|
|
|
|
WARN(skb_get_queue_mapping(skb) > priv->tx_cfg.num_queues,
|
|
"skb queue index out of range");
|
|
tx = &priv->tx[skb_get_queue_mapping(skb)];
|
|
if (unlikely(gve_maybe_stop_tx(tx, skb))) {
|
|
/* We need to ring the txq doorbell -- we have stopped the Tx
|
|
* queue for want of resources, but prior calls to gve_tx()
|
|
* may have added descriptors without ringing the doorbell.
|
|
*/
|
|
|
|
gve_tx_put_doorbell(priv, tx->q_resources, tx->req);
|
|
return NETDEV_TX_BUSY;
|
|
}
|
|
nsegs = gve_tx_add_skb(tx, skb, &priv->pdev->dev);
|
|
|
|
netdev_tx_sent_queue(tx->netdev_txq, skb->len);
|
|
skb_tx_timestamp(skb);
|
|
|
|
/* give packets to NIC */
|
|
tx->req += nsegs;
|
|
|
|
if (!netif_xmit_stopped(tx->netdev_txq) && netdev_xmit_more())
|
|
return NETDEV_TX_OK;
|
|
|
|
gve_tx_put_doorbell(priv, tx->q_resources, tx->req);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
#define GVE_TX_START_THRESH PAGE_SIZE
|
|
|
|
static int gve_clean_tx_done(struct gve_priv *priv, struct gve_tx_ring *tx,
|
|
u32 to_do, bool try_to_wake)
|
|
{
|
|
struct gve_tx_buffer_state *info;
|
|
u64 pkts = 0, bytes = 0;
|
|
size_t space_freed = 0;
|
|
struct sk_buff *skb;
|
|
int i, j;
|
|
u32 idx;
|
|
|
|
for (j = 0; j < to_do; j++) {
|
|
idx = tx->done & tx->mask;
|
|
netif_info(priv, tx_done, priv->dev,
|
|
"[%d] %s: idx=%d (req=%u done=%u)\n",
|
|
tx->q_num, __func__, idx, tx->req, tx->done);
|
|
info = &tx->info[idx];
|
|
skb = info->skb;
|
|
|
|
/* Mark as free */
|
|
if (skb) {
|
|
info->skb = NULL;
|
|
bytes += skb->len;
|
|
pkts++;
|
|
dev_consume_skb_any(skb);
|
|
/* FIFO free */
|
|
for (i = 0; i < ARRAY_SIZE(info->iov); i++) {
|
|
space_freed += info->iov[i].iov_len +
|
|
info->iov[i].iov_padding;
|
|
info->iov[i].iov_len = 0;
|
|
info->iov[i].iov_padding = 0;
|
|
}
|
|
}
|
|
tx->done++;
|
|
}
|
|
|
|
gve_tx_free_fifo(&tx->tx_fifo, space_freed);
|
|
u64_stats_update_begin(&tx->statss);
|
|
tx->bytes_done += bytes;
|
|
tx->pkt_done += pkts;
|
|
u64_stats_update_end(&tx->statss);
|
|
netdev_tx_completed_queue(tx->netdev_txq, pkts, bytes);
|
|
|
|
/* start the queue if we've stopped it */
|
|
#ifndef CONFIG_BQL
|
|
/* Make sure that the doorbells are synced */
|
|
smp_mb();
|
|
#endif
|
|
if (try_to_wake && netif_tx_queue_stopped(tx->netdev_txq) &&
|
|
likely(gve_can_tx(tx, GVE_TX_START_THRESH))) {
|
|
tx->wake_queue++;
|
|
netif_tx_wake_queue(tx->netdev_txq);
|
|
}
|
|
|
|
return pkts;
|
|
}
|
|
|
|
__be32 gve_tx_load_event_counter(struct gve_priv *priv,
|
|
struct gve_tx_ring *tx)
|
|
{
|
|
u32 counter_index = be32_to_cpu((tx->q_resources->counter_index));
|
|
|
|
return READ_ONCE(priv->counter_array[counter_index]);
|
|
}
|
|
|
|
bool gve_tx_poll(struct gve_notify_block *block, int budget)
|
|
{
|
|
struct gve_priv *priv = block->priv;
|
|
struct gve_tx_ring *tx = block->tx;
|
|
bool repoll = false;
|
|
u32 nic_done;
|
|
u32 to_do;
|
|
|
|
/* If budget is 0, do all the work */
|
|
if (budget == 0)
|
|
budget = INT_MAX;
|
|
|
|
/* Find out how much work there is to be done */
|
|
tx->last_nic_done = gve_tx_load_event_counter(priv, tx);
|
|
nic_done = be32_to_cpu(tx->last_nic_done);
|
|
if (budget > 0) {
|
|
/* Do as much work as we have that the budget will
|
|
* allow
|
|
*/
|
|
to_do = min_t(u32, (nic_done - tx->done), budget);
|
|
gve_clean_tx_done(priv, tx, to_do, true);
|
|
}
|
|
/* If we still have work we want to repoll */
|
|
repoll |= (nic_done != tx->done);
|
|
return repoll;
|
|
}
|