548 lines
17 KiB
C
548 lines
17 KiB
C
/* Copyright 2008-2013 Broadcom Corporation
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* Copyright (c) 2014 QLogic Corporation
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* All rights reserved
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*
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* Unless you and QLogic execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available
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* at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Qlogic software provided under a
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* license other than the GPL, without Qlogic's express prior written
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* consent.
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*
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* Written by Yaniv Rosner
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*
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*/
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#ifndef BNX2X_LINK_H
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#define BNX2X_LINK_H
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/***********************************************************/
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/* Defines */
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/***********************************************************/
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#define DEFAULT_PHY_DEV_ADDR 3
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#define E2_DEFAULT_PHY_DEV_ADDR 5
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#define BNX2X_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
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#define BNX2X_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
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#define BNX2X_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
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#define BNX2X_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
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#define BNX2X_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
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#define NET_SERDES_IF_XFI 1
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#define NET_SERDES_IF_SFI 2
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#define NET_SERDES_IF_KR 3
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#define NET_SERDES_IF_DXGXS 4
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#define SPEED_AUTO_NEG 0
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#define SPEED_20000 20000
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#define I2C_DEV_ADDR_A0 0xa0
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#define I2C_DEV_ADDR_A2 0xa2
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#define SFP_EEPROM_PAGE_SIZE 16
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#define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
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#define SFP_EEPROM_VENDOR_NAME_SIZE 16
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#define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
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#define SFP_EEPROM_VENDOR_OUI_SIZE 3
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#define SFP_EEPROM_PART_NO_ADDR 0x28
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#define SFP_EEPROM_PART_NO_SIZE 16
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#define SFP_EEPROM_REVISION_ADDR 0x38
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#define SFP_EEPROM_REVISION_SIZE 4
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#define SFP_EEPROM_SERIAL_ADDR 0x44
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#define SFP_EEPROM_SERIAL_SIZE 16
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#define SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
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#define SFP_EEPROM_DATE_SIZE 6
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#define SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
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#define SFP_EEPROM_DIAG_TYPE_SIZE 1
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#define SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
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#define SFP_EEPROM_DDM_IMPLEMENTED (1<<6)
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#define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
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#define SFP_EEPROM_SFF_8472_COMP_SIZE 1
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#define SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
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#define SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
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#define PWR_FLT_ERR_MSG_LEN 250
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#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
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((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
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#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
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(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
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#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
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((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
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/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
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#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
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/* Single Media board contains single external phy */
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#define SINGLE_MEDIA(params) (params->num_phys == 2)
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/* Dual Media board contains two external phy with different media */
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#define DUAL_MEDIA(params) (params->num_phys == 3)
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#define FW_PARAM_PHY_ADDR_MASK 0x000000FF
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#define FW_PARAM_PHY_TYPE_MASK 0x0000FF00
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#define FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
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#define FW_PARAM_MDIO_CTRL_OFFSET 16
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#define FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
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FW_PARAM_PHY_ADDR_MASK)
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#define FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
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FW_PARAM_PHY_TYPE_MASK)
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#define FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
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FW_PARAM_MDIO_CTRL_MASK) >> \
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FW_PARAM_MDIO_CTRL_OFFSET)
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#define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
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(phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
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#define PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
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#define PFC_BRB_FULL_LB_XON_THRESHOLD 250
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#define MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
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#define BMAC_CONTROL_RX_ENABLE 2
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/***********************************************************/
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/* Structs */
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/***********************************************************/
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#define INT_PHY 0
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#define EXT_PHY1 1
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#define EXT_PHY2 2
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#define MAX_PHYS 3
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/* Same configuration is shared between the XGXS and the first external phy */
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#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
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#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
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0 : (_phy_idx - 1))
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/***********************************************************/
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/* bnx2x_phy struct */
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/* Defines the required arguments and function per phy */
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/***********************************************************/
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struct link_vars;
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struct link_params;
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struct bnx2x_phy;
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typedef u8 (*config_init_t)(struct bnx2x_phy *phy, struct link_params *params,
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struct link_vars *vars);
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typedef u8 (*read_status_t)(struct bnx2x_phy *phy, struct link_params *params,
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struct link_vars *vars);
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typedef void (*link_reset_t)(struct bnx2x_phy *phy,
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struct link_params *params);
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typedef void (*config_loopback_t)(struct bnx2x_phy *phy,
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struct link_params *params);
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typedef u8 (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
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typedef void (*hw_reset_t)(struct bnx2x_phy *phy, struct link_params *params);
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typedef void (*set_link_led_t)(struct bnx2x_phy *phy,
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struct link_params *params, u8 mode);
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typedef void (*phy_specific_func_t)(struct bnx2x_phy *phy,
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struct link_params *params, u32 action);
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struct bnx2x_reg_set {
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u8 devad;
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u16 reg;
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u16 val;
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};
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struct bnx2x_phy {
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u32 type;
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/* Loaded during init */
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u8 addr;
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u8 def_md_devad;
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u16 flags;
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/* No Over-Current detection */
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#define FLAGS_NOC (1<<1)
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/* Fan failure detection required */
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#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
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/* Initialize first the XGXS and only then the phy itself */
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#define FLAGS_INIT_XGXS_FIRST (1<<3)
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#define FLAGS_WC_DUAL_MODE (1<<4)
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#define FLAGS_4_PORT_MODE (1<<5)
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#define FLAGS_REARM_LATCH_SIGNAL (1<<6)
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#define FLAGS_SFP_NOT_APPROVED (1<<7)
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#define FLAGS_MDC_MDIO_WA (1<<8)
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#define FLAGS_DUMMY_READ (1<<9)
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#define FLAGS_MDC_MDIO_WA_B0 (1<<10)
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#define FLAGS_TX_ERROR_CHECK (1<<12)
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#define FLAGS_EEE (1<<13)
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#define FLAGS_MDC_MDIO_WA_G (1<<15)
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/* preemphasis values for the rx side */
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u16 rx_preemphasis[4];
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/* preemphasis values for the tx side */
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u16 tx_preemphasis[4];
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/* EMAC address for access MDIO */
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u32 mdio_ctrl;
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u32 supported;
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u32 media_type;
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#define ETH_PHY_UNSPECIFIED 0x0
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#define ETH_PHY_SFPP_10G_FIBER 0x1
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#define ETH_PHY_XFP_FIBER 0x2
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#define ETH_PHY_DA_TWINAX 0x3
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#define ETH_PHY_BASE_T 0x4
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#define ETH_PHY_SFP_1G_FIBER 0x5
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#define ETH_PHY_KR 0xf0
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#define ETH_PHY_CX4 0xf1
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#define ETH_PHY_NOT_PRESENT 0xff
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/* The address in which version is located*/
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u32 ver_addr;
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u16 req_flow_ctrl;
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u16 req_line_speed;
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u32 speed_cap_mask;
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u16 req_duplex;
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u16 rsrv;
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/* Called per phy/port init, and it configures LASI, speed, autoneg,
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duplex, flow control negotiation, etc. */
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config_init_t config_init;
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/* Called due to interrupt. It determines the link, speed */
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read_status_t read_status;
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/* Called when driver is unloading. Should reset the phy */
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link_reset_t link_reset;
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/* Set the loopback configuration for the phy */
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config_loopback_t config_loopback;
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/* Format the given raw number into str up to len */
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format_fw_ver_t format_fw_ver;
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/* Reset the phy (both ports) */
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hw_reset_t hw_reset;
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/* Set link led mode (on/off/oper)*/
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set_link_led_t set_link_led;
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/* PHY Specific tasks */
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phy_specific_func_t phy_specific_func;
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#define DISABLE_TX 1
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#define ENABLE_TX 2
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#define PHY_INIT 3
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};
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/* Inputs parameters to the CLC */
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struct link_params {
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u8 port;
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/* Default / User Configuration */
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u8 loopback_mode;
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#define LOOPBACK_NONE 0
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#define LOOPBACK_EMAC 1
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#define LOOPBACK_BMAC 2
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#define LOOPBACK_XGXS 3
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#define LOOPBACK_EXT_PHY 4
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#define LOOPBACK_EXT 5
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#define LOOPBACK_UMAC 6
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#define LOOPBACK_XMAC 7
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/* Device parameters */
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u8 mac_addr[6];
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u16 req_duplex[LINK_CONFIG_SIZE];
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u16 req_flow_ctrl[LINK_CONFIG_SIZE];
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u16 req_line_speed[LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
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/* shmem parameters */
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u32 shmem_base;
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u32 shmem2_base;
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u32 speed_cap_mask[LINK_CONFIG_SIZE];
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u32 switch_cfg;
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#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
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#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
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#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
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u32 lane_config;
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/* Phy register parameter */
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u32 chip_id;
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/* features */
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u32 feature_config_flags;
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#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
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#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
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#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
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#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
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#define FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
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#define FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
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#define FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
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#define FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
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#define FEATURE_CONFIG_MT_SUPPORT (1<<13)
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#define FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
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/* Will be populated during common init */
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struct bnx2x_phy phy[MAX_PHYS];
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/* Will be populated during common init */
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u8 num_phys;
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u8 rsrv;
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/* Used to configure the EEE Tx LPI timer, has several modes of
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* operation, according to bits 29:28 -
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* 2'b00: Timer will be configured by nvram, output will be the value
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* from nvram.
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* 2'b01: Timer will be configured by nvram, output will be in
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* microseconds.
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* 2'b10: bits 1:0 contain an nvram value which will be used instead
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* of the one located in the nvram. Output will be that value.
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* 2'b11: bits 19:0 contain the idle timer in microseconds; output
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* will be in microseconds.
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* Bits 31:30 should be 2'b11 in order for EEE to be enabled.
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*/
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u32 eee_mode;
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#define EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
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#define EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
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#define EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
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#define EEE_MODE_NVRAM_MASK (0x3)
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#define EEE_MODE_TIMER_MASK (0xfffff)
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#define EEE_MODE_OUTPUT_TIME (1<<28)
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#define EEE_MODE_OVERRIDE_NVRAM (1<<29)
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#define EEE_MODE_ENABLE_LPI (1<<30)
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#define EEE_MODE_ADV_LPI (1<<31)
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u16 hw_led_mode; /* part of the hw_config read from the shmem */
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u32 multi_phy_config;
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/* Device pointer passed to all callback functions */
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struct bnx2x *bp;
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u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
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req_flow_ctrl is set to AUTO */
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u16 link_flags;
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#define LINK_FLAGS_INT_DISABLED (1<<0)
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#define PHY_INITIALIZED (1<<1)
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u32 lfa_base;
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/* The same definitions as the shmem2 parameter */
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u32 link_attr_sync;
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};
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/* Output parameters */
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struct link_vars {
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u8 phy_flags;
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#define PHY_XGXS_FLAG (1<<0)
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#define PHY_SGMII_FLAG (1<<1)
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#define PHY_PHYSICAL_LINK_FLAG (1<<2)
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#define PHY_HALF_OPEN_CONN_FLAG (1<<3)
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#define PHY_OVER_CURRENT_FLAG (1<<4)
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#define PHY_SFP_TX_FAULT_FLAG (1<<5)
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u8 mac_type;
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#define MAC_TYPE_NONE 0
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#define MAC_TYPE_EMAC 1
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#define MAC_TYPE_BMAC 2
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#define MAC_TYPE_UMAC 3
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#define MAC_TYPE_XMAC 4
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u8 phy_link_up; /* internal phy link indication */
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u8 link_up;
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u16 line_speed;
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u16 duplex;
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u16 flow_ctrl;
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u16 ieee_fc;
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/* The same definitions as the shmem parameter */
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u32 link_status;
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u32 eee_status;
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u8 fault_detected;
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u8 check_kr2_recovery_cnt;
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#define CHECK_KR2_RECOVERY_CNT 5
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u16 periodic_flags;
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#define PERIODIC_FLAGS_LINK_EVENT 0x0001
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u32 aeu_int_mask;
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u8 rx_tx_asic_rst;
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u8 turn_to_run_wc_rt;
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u16 rsrv2;
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};
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/***********************************************************/
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/* Functions */
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/***********************************************************/
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int bnx2x_phy_init(struct link_params *params, struct link_vars *vars);
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/* Reset the link. Should be called when driver or interface goes down
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Before calling phy firmware upgrade, the reset_ext_phy should be set
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to 0 */
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int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
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u8 reset_ext_phy);
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int bnx2x_lfa_reset(struct link_params *params, struct link_vars *vars);
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/* bnx2x_link_update should be called upon link interrupt */
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int bnx2x_link_update(struct link_params *params, struct link_vars *vars);
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/* use the following phy functions to read/write from external_phy
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In order to use it to read/write internal phy registers, use
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DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
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the register */
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int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
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u8 devad, u16 reg, u16 *ret_val);
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int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
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u8 devad, u16 reg, u16 val);
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/* Reads the link_status from the shmem,
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and update the link vars accordingly */
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void bnx2x_link_status_update(struct link_params *input,
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struct link_vars *output);
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/* returns string representing the fw_version of the external phy */
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int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
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u16 len);
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/* Set/Unset the led
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Basically, the CLC takes care of the led for the link, but in case one needs
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to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to
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blink the led, and LED_MODE_OFF to set the led off.*/
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int bnx2x_set_led(struct link_params *params,
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struct link_vars *vars, u8 mode, u32 speed);
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#define LED_MODE_OFF 0
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#define LED_MODE_ON 1
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#define LED_MODE_OPER 2
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#define LED_MODE_FRONT_PANEL_OFF 3
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/* bnx2x_handle_module_detect_int should be called upon module detection
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interrupt */
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void bnx2x_handle_module_detect_int(struct link_params *params);
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/* Get the actual link status. In case it returns 0, link is up,
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otherwise link is down*/
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int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
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u8 is_serdes);
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/* One-time initialization for external phy after power up */
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int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
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u32 shmem2_base_path[], u32 chip_id);
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/* Reset the external PHY using GPIO */
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void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port);
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/* Reset the external of SFX7101 */
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void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy);
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/* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
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int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
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struct link_params *params, u8 dev_addr,
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u16 addr, u16 byte_cnt, u8 *o_buf);
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void bnx2x_hw_reset_phy(struct link_params *params);
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/* Check swap bit and adjust PHY order */
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u32 bnx2x_phy_selection(struct link_params *params);
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/* Probe the phys on board, and populate them in "params" */
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int bnx2x_phy_probe(struct link_params *params);
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/* Checks if fan failure detection is required on one of the phys on board */
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u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
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u32 shmem2_base, u8 port);
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/* Open / close the gate between the NIG and the BRB */
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void bnx2x_set_rx_filter(struct link_params *params, u8 en);
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/* DCBX structs */
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/* Number of maximum COS per chip */
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#define DCBX_E2E3_MAX_NUM_COS (2)
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#define DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
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#define DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
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#define DCBX_E3B0_MAX_NUM_COS ( \
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MAXVAL(DCBX_E3B0_MAX_NUM_COS_PORT0, \
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DCBX_E3B0_MAX_NUM_COS_PORT1))
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#define DCBX_MAX_NUM_COS ( \
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MAXVAL(DCBX_E3B0_MAX_NUM_COS, \
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DCBX_E2E3_MAX_NUM_COS))
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/* PFC port configuration params */
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struct bnx2x_nig_brb_pfc_port_params {
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/* NIG */
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u32 pause_enable;
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u32 llfc_out_en;
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u32 llfc_enable;
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u32 pkt_priority_to_cos;
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u8 num_of_rx_cos_priority_mask;
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u32 rx_cos_priority_mask[DCBX_MAX_NUM_COS];
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u32 llfc_high_priority_classes;
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u32 llfc_low_priority_classes;
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};
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/* ETS port configuration params */
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struct bnx2x_ets_bw_params {
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u8 bw;
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};
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struct bnx2x_ets_sp_params {
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/**
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* valid values are 0 - 5. 0 is highest strict priority.
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* There can't be two COS's with the same pri.
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*/
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u8 pri;
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};
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enum bnx2x_cos_state {
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bnx2x_cos_state_strict = 0,
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bnx2x_cos_state_bw = 1,
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};
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struct bnx2x_ets_cos_params {
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enum bnx2x_cos_state state ;
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union {
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struct bnx2x_ets_bw_params bw_params;
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struct bnx2x_ets_sp_params sp_params;
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} params;
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};
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struct bnx2x_ets_params {
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u8 num_of_cos; /* Number of valid COS entries*/
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struct bnx2x_ets_cos_params cos[DCBX_MAX_NUM_COS];
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};
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/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
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* when link is already up
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*/
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int bnx2x_update_pfc(struct link_params *params,
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struct link_vars *vars,
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struct bnx2x_nig_brb_pfc_port_params *pfc_params);
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/* Used to configure the ETS to disable */
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int bnx2x_ets_disabled(struct link_params *params,
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struct link_vars *vars);
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/* Used to configure the ETS to BW limited */
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void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
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const u32 cos1_bw);
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/* Used to configure the ETS to strict */
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int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
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/* Configure the COS to ETS according to BW and SP settings.*/
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int bnx2x_ets_e3b0_config(const struct link_params *params,
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const struct link_vars *vars,
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struct bnx2x_ets_params *ets_params);
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void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
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u32 chip_id, u32 shmem_base, u32 shmem2_base,
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u8 port);
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void bnx2x_period_func(struct link_params *params, struct link_vars *vars);
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#endif /* BNX2X_LINK_H */
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