696 lines
19 KiB
C
696 lines
19 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2016-2018, NXP Semiconductors
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* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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#include <linux/packing.h>
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#include "sja1105.h"
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#define SJA1105_SIZE_CGU_CMD 4
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struct sja1105_cfg_pad_mii_tx {
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u64 d32_os;
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u64 d32_ipud;
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u64 d10_os;
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u64 d10_ipud;
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u64 ctrl_os;
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u64 ctrl_ipud;
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u64 clk_os;
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u64 clk_ih;
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u64 clk_ipud;
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};
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struct sja1105_cfg_pad_mii_id {
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u64 rxc_stable_ovr;
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u64 rxc_delay;
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u64 rxc_bypass;
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u64 rxc_pd;
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u64 txc_stable_ovr;
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u64 txc_delay;
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u64 txc_bypass;
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u64 txc_pd;
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};
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/* UM10944 Table 82.
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* IDIV_0_C to IDIV_4_C control registers
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* (addr. 10000Bh to 10000Fh)
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*/
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struct sja1105_cgu_idiv {
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u64 clksrc;
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u64 autoblock;
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u64 idiv;
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u64 pd;
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};
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/* PLL_1_C control register
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*
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* SJA1105 E/T: UM10944 Table 81 (address 10000Ah)
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* SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah)
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*/
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struct sja1105_cgu_pll_ctrl {
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u64 pllclksrc;
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u64 msel;
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u64 autoblock;
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u64 psel;
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u64 direct;
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u64 fbsel;
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u64 bypass;
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u64 pd;
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};
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enum {
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CLKSRC_MII0_TX_CLK = 0x00,
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CLKSRC_MII0_RX_CLK = 0x01,
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CLKSRC_MII1_TX_CLK = 0x02,
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CLKSRC_MII1_RX_CLK = 0x03,
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CLKSRC_MII2_TX_CLK = 0x04,
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CLKSRC_MII2_RX_CLK = 0x05,
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CLKSRC_MII3_TX_CLK = 0x06,
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CLKSRC_MII3_RX_CLK = 0x07,
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CLKSRC_MII4_TX_CLK = 0x08,
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CLKSRC_MII4_RX_CLK = 0x09,
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CLKSRC_PLL0 = 0x0B,
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CLKSRC_PLL1 = 0x0E,
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CLKSRC_IDIV0 = 0x11,
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CLKSRC_IDIV1 = 0x12,
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CLKSRC_IDIV2 = 0x13,
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CLKSRC_IDIV3 = 0x14,
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CLKSRC_IDIV4 = 0x15,
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};
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/* UM10944 Table 83.
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* MIIx clock control registers 1 to 30
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* (addresses 100013h to 100035h)
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*/
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struct sja1105_cgu_mii_ctrl {
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u64 clksrc;
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u64 autoblock;
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u64 pd;
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};
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static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv,
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enum packing_op op)
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{
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const int size = 4;
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sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op);
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sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op);
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sja1105_packing(buf, &idiv->idiv, 5, 2, size, op);
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sja1105_packing(buf, &idiv->pd, 0, 0, size, op);
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}
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static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
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bool enabled, int factor)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct device *dev = priv->ds->dev;
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struct sja1105_cgu_idiv idiv;
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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if (enabled && factor != 1 && factor != 10) {
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dev_err(dev, "idiv factor must be 1 or 10\n");
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return -ERANGE;
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}
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/* Payload for packed_buf */
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idiv.clksrc = 0x0A; /* 25MHz */
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idiv.autoblock = 1; /* Block clk automatically */
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idiv.idiv = factor - 1; /* Divide by 1 or 10 */
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idiv.pd = enabled ? 0 : 1; /* Power down? */
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sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->cgu_idiv[port], packed_buf,
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SJA1105_SIZE_CGU_CMD);
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}
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static void
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sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd,
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enum packing_op op)
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{
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const int size = 4;
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sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op);
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sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
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sja1105_packing(buf, &cmd->pd, 0, 0, size, op);
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}
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static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
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int port, sja1105_mii_role_t role)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cgu_mii_ctrl mii_tx_clk;
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const int mac_clk_sources[] = {
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CLKSRC_MII0_TX_CLK,
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CLKSRC_MII1_TX_CLK,
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CLKSRC_MII2_TX_CLK,
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CLKSRC_MII3_TX_CLK,
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CLKSRC_MII4_TX_CLK,
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};
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const int phy_clk_sources[] = {
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CLKSRC_IDIV0,
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CLKSRC_IDIV1,
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CLKSRC_IDIV2,
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CLKSRC_IDIV3,
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CLKSRC_IDIV4,
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};
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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int clksrc;
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if (role == XMII_MAC)
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clksrc = mac_clk_sources[port];
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else
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clksrc = phy_clk_sources[port];
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/* Payload for packed_buf */
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mii_tx_clk.clksrc = clksrc;
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mii_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
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mii_tx_clk.pd = 0; /* Power Down off => enabled */
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sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->mii_tx_clk[port], packed_buf,
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SJA1105_SIZE_CGU_CMD);
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}
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static int
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sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cgu_mii_ctrl mii_rx_clk;
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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const int clk_sources[] = {
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CLKSRC_MII0_RX_CLK,
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CLKSRC_MII1_RX_CLK,
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CLKSRC_MII2_RX_CLK,
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CLKSRC_MII3_RX_CLK,
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CLKSRC_MII4_RX_CLK,
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};
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/* Payload for packed_buf */
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mii_rx_clk.clksrc = clk_sources[port];
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mii_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
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mii_rx_clk.pd = 0; /* Power Down off => enabled */
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sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->mii_rx_clk[port], packed_buf,
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SJA1105_SIZE_CGU_CMD);
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}
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static int
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sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cgu_mii_ctrl mii_ext_tx_clk;
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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const int clk_sources[] = {
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CLKSRC_IDIV0,
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CLKSRC_IDIV1,
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CLKSRC_IDIV2,
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CLKSRC_IDIV3,
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CLKSRC_IDIV4,
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};
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/* Payload for packed_buf */
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mii_ext_tx_clk.clksrc = clk_sources[port];
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mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
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mii_ext_tx_clk.pd = 0; /* Power Down off => enabled */
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sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->mii_ext_tx_clk[port],
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packed_buf, SJA1105_SIZE_CGU_CMD);
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}
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static int
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sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cgu_mii_ctrl mii_ext_rx_clk;
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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const int clk_sources[] = {
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CLKSRC_IDIV0,
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CLKSRC_IDIV1,
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CLKSRC_IDIV2,
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CLKSRC_IDIV3,
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CLKSRC_IDIV4,
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};
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/* Payload for packed_buf */
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mii_ext_rx_clk.clksrc = clk_sources[port];
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mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
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mii_ext_rx_clk.pd = 0; /* Power Down off => enabled */
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sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->mii_ext_rx_clk[port],
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packed_buf, SJA1105_SIZE_CGU_CMD);
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}
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static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port,
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sja1105_mii_role_t role)
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{
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struct device *dev = priv->ds->dev;
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int rc;
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dev_dbg(dev, "Configuring MII-%s clocking\n",
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(role == XMII_MAC) ? "MAC" : "PHY");
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/* If role is MAC, disable IDIV
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* If role is PHY, enable IDIV and configure for 1/1 divider
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*/
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rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1);
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if (rc < 0)
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return rc;
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/* Configure CLKSRC of MII_TX_CLK_n
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* * If role is MAC, select TX_CLK_n
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* * If role is PHY, select IDIV_n
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*/
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rc = sja1105_cgu_mii_tx_clk_config(priv, port, role);
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if (rc < 0)
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return rc;
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/* Configure CLKSRC of MII_RX_CLK_n
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* Select RX_CLK_n
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*/
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rc = sja1105_cgu_mii_rx_clk_config(priv, port);
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if (rc < 0)
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return rc;
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if (role == XMII_PHY) {
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/* Per MII spec, the PHY (which is us) drives the TX_CLK pin */
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/* Configure CLKSRC of EXT_TX_CLK_n
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* Select IDIV_n
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*/
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rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port);
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if (rc < 0)
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return rc;
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/* Configure CLKSRC of EXT_RX_CLK_n
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* Select IDIV_n
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*/
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rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port);
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if (rc < 0)
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return rc;
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}
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return 0;
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}
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static void
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sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd,
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enum packing_op op)
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{
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const int size = 4;
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sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op);
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sja1105_packing(buf, &cmd->msel, 23, 16, size, op);
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sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op);
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sja1105_packing(buf, &cmd->psel, 9, 8, size, op);
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sja1105_packing(buf, &cmd->direct, 7, 7, size, op);
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sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op);
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sja1105_packing(buf, &cmd->bypass, 1, 1, size, op);
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sja1105_packing(buf, &cmd->pd, 0, 0, size, op);
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}
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static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
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int port, sja1105_speed_t speed)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cgu_mii_ctrl txc;
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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int clksrc;
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if (speed == SJA1105_SPEED_1000MBPS) {
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clksrc = CLKSRC_PLL0;
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} else {
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int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2,
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CLKSRC_IDIV3, CLKSRC_IDIV4};
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clksrc = clk_sources[port];
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}
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/* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */
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txc.clksrc = clksrc;
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/* Autoblock clk while changing clksrc */
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txc.autoblock = 1;
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/* Power Down off => enabled */
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txc.pd = 0;
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sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->rgmii_tx_clk[port],
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packed_buf, SJA1105_SIZE_CGU_CMD);
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}
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/* AGU */
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static void
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sja1105_cfg_pad_mii_tx_packing(void *buf, struct sja1105_cfg_pad_mii_tx *cmd,
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enum packing_op op)
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{
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const int size = 4;
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sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op);
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sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op);
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sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op);
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sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op);
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sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op);
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sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op);
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sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op);
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sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op);
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sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op);
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}
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static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
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int port)
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{
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cfg_pad_mii_tx pad_mii_tx;
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u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
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/* Payload */
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pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */
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/* high noise/high speed */
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pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */
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/* high noise/high speed */
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pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */
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/* plain input (default) */
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pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */
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/* plain input (default) */
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pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */
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pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */
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pad_mii_tx.clk_os = 3; /* TX_CLK output stage */
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pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */
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pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */
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sja1105_cfg_pad_mii_tx_packing(packed_buf, &pad_mii_tx, PACK);
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return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
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regs->pad_mii_tx[port],
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packed_buf, SJA1105_SIZE_CGU_CMD);
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}
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static void
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sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
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enum packing_op op)
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{
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const int size = SJA1105_SIZE_CGU_CMD;
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sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op);
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sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op);
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sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op);
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sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op);
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sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op);
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sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op);
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sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op);
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sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op);
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}
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/* Valid range in degrees is an integer between 73.8 and 101.7 */
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static inline u64 sja1105_rgmii_delay(u64 phase)
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{
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/* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9.
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* To avoid floating point operations we'll multiply by 10
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* and get 1 decimal point precision.
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*/
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phase *= 10;
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return (phase - 738) / 9;
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}
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/* The RGMII delay setup procedure is 2-step and gets called upon each
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* .phylink_mac_config. Both are strategic.
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* The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues
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* with recovering from a frequency change of the link partner's RGMII clock.
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* The easiest way to recover from this is to temporarily power down the TDL,
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* as it will re-lock at the new frequency afterwards.
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*/
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int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
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{
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const struct sja1105_private *priv = ctx;
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const struct sja1105_regs *regs = priv->info->regs;
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struct sja1105_cfg_pad_mii_id pad_mii_id = {0};
|
|
u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
|
|
int rc;
|
|
|
|
if (priv->rgmii_rx_delay[port])
|
|
pad_mii_id.rxc_delay = sja1105_rgmii_delay(90);
|
|
if (priv->rgmii_tx_delay[port])
|
|
pad_mii_id.txc_delay = sja1105_rgmii_delay(90);
|
|
|
|
/* Stage 1: Turn the RGMII delay lines off. */
|
|
pad_mii_id.rxc_bypass = 1;
|
|
pad_mii_id.rxc_pd = 1;
|
|
pad_mii_id.txc_bypass = 1;
|
|
pad_mii_id.txc_pd = 1;
|
|
sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
|
|
|
|
rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE,
|
|
regs->pad_mii_id[port],
|
|
packed_buf, SJA1105_SIZE_CGU_CMD);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
/* Stage 2: Turn the RGMII delay lines on. */
|
|
if (priv->rgmii_rx_delay[port]) {
|
|
pad_mii_id.rxc_bypass = 0;
|
|
pad_mii_id.rxc_pd = 0;
|
|
}
|
|
if (priv->rgmii_tx_delay[port]) {
|
|
pad_mii_id.txc_bypass = 0;
|
|
pad_mii_id.txc_pd = 0;
|
|
}
|
|
sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);
|
|
|
|
return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
|
|
regs->pad_mii_id[port],
|
|
packed_buf, SJA1105_SIZE_CGU_CMD);
|
|
}
|
|
|
|
static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port,
|
|
sja1105_mii_role_t role)
|
|
{
|
|
struct device *dev = priv->ds->dev;
|
|
struct sja1105_mac_config_entry *mac;
|
|
sja1105_speed_t speed;
|
|
int rc;
|
|
|
|
mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
|
|
speed = mac[port].speed;
|
|
|
|
dev_dbg(dev, "Configuring port %d RGMII at speed %dMbps\n",
|
|
port, speed);
|
|
|
|
switch (speed) {
|
|
case SJA1105_SPEED_1000MBPS:
|
|
/* 1000Mbps, IDIV disabled (125 MHz) */
|
|
rc = sja1105_cgu_idiv_config(priv, port, false, 1);
|
|
break;
|
|
case SJA1105_SPEED_100MBPS:
|
|
/* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */
|
|
rc = sja1105_cgu_idiv_config(priv, port, true, 1);
|
|
break;
|
|
case SJA1105_SPEED_10MBPS:
|
|
/* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */
|
|
rc = sja1105_cgu_idiv_config(priv, port, true, 10);
|
|
break;
|
|
case SJA1105_SPEED_AUTO:
|
|
/* Skip CGU configuration if there is no speed available
|
|
* (e.g. link is not established yet)
|
|
*/
|
|
dev_dbg(dev, "Speed not available, skipping CGU config\n");
|
|
return 0;
|
|
default:
|
|
rc = -EINVAL;
|
|
}
|
|
|
|
if (rc < 0) {
|
|
dev_err(dev, "Failed to configure idiv\n");
|
|
return rc;
|
|
}
|
|
rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed);
|
|
if (rc < 0) {
|
|
dev_err(dev, "Failed to configure RGMII Tx clock\n");
|
|
return rc;
|
|
}
|
|
rc = sja1105_rgmii_cfg_pad_tx_config(priv, port);
|
|
if (rc < 0) {
|
|
dev_err(dev, "Failed to configure Tx pad registers\n");
|
|
return rc;
|
|
}
|
|
if (!priv->info->setup_rgmii_delay)
|
|
return 0;
|
|
/* The role has no hardware effect for RGMII. However we use it as
|
|
* a proxy for this interface being a MAC-to-MAC connection, with
|
|
* the RGMII internal delays needing to be applied by us.
|
|
*/
|
|
if (role == XMII_MAC)
|
|
return 0;
|
|
|
|
return priv->info->setup_rgmii_delay(priv, port);
|
|
}
|
|
|
|
static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
|
|
int port)
|
|
{
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
struct sja1105_cgu_mii_ctrl ref_clk;
|
|
u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
|
|
const int clk_sources[] = {
|
|
CLKSRC_MII0_TX_CLK,
|
|
CLKSRC_MII1_TX_CLK,
|
|
CLKSRC_MII2_TX_CLK,
|
|
CLKSRC_MII3_TX_CLK,
|
|
CLKSRC_MII4_TX_CLK,
|
|
};
|
|
|
|
/* Payload for packed_buf */
|
|
ref_clk.clksrc = clk_sources[port];
|
|
ref_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
|
|
ref_clk.pd = 0; /* Power Down off => enabled */
|
|
sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);
|
|
|
|
return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
|
|
regs->rmii_ref_clk[port],
|
|
packed_buf, SJA1105_SIZE_CGU_CMD);
|
|
}
|
|
|
|
static int
|
|
sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
|
|
{
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
struct sja1105_cgu_mii_ctrl ext_tx_clk;
|
|
u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
|
|
|
|
/* Payload for packed_buf */
|
|
ext_tx_clk.clksrc = CLKSRC_PLL1;
|
|
ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */
|
|
ext_tx_clk.pd = 0; /* Power Down off => enabled */
|
|
sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK);
|
|
|
|
return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
|
|
regs->rmii_ext_tx_clk[port],
|
|
packed_buf, SJA1105_SIZE_CGU_CMD);
|
|
}
|
|
|
|
static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
|
|
{
|
|
const struct sja1105_regs *regs = priv->info->regs;
|
|
u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0};
|
|
struct sja1105_cgu_pll_ctrl pll = {0};
|
|
struct device *dev = priv->ds->dev;
|
|
int rc;
|
|
|
|
/* PLL1 must be enabled and output 50 Mhz.
|
|
* This is done by writing first 0x0A010941 to
|
|
* the PLL_1_C register and then deasserting
|
|
* power down (PD) 0x0A010940.
|
|
*/
|
|
|
|
/* Step 1: PLL1 setup for 50Mhz */
|
|
pll.pllclksrc = 0xA;
|
|
pll.msel = 0x1;
|
|
pll.autoblock = 0x1;
|
|
pll.psel = 0x1;
|
|
pll.direct = 0x0;
|
|
pll.fbsel = 0x1;
|
|
pll.bypass = 0x0;
|
|
pll.pd = 0x1;
|
|
|
|
sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
|
|
rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rmii_pll1,
|
|
packed_buf, SJA1105_SIZE_CGU_CMD);
|
|
if (rc < 0) {
|
|
dev_err(dev, "failed to configure PLL1 for 50MHz\n");
|
|
return rc;
|
|
}
|
|
|
|
/* Step 2: Enable PLL1 */
|
|
pll.pd = 0x0;
|
|
|
|
sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
|
|
rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rmii_pll1,
|
|
packed_buf, SJA1105_SIZE_CGU_CMD);
|
|
if (rc < 0) {
|
|
dev_err(dev, "failed to enable PLL1\n");
|
|
return rc;
|
|
}
|
|
return rc;
|
|
}
|
|
|
|
static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port,
|
|
sja1105_mii_role_t role)
|
|
{
|
|
struct device *dev = priv->ds->dev;
|
|
int rc;
|
|
|
|
dev_dbg(dev, "Configuring RMII-%s clocking\n",
|
|
(role == XMII_MAC) ? "MAC" : "PHY");
|
|
/* AH1601.pdf chapter 2.5.1. Sources */
|
|
if (role == XMII_MAC) {
|
|
/* Configure and enable PLL1 for 50Mhz output */
|
|
rc = sja1105_cgu_rmii_pll_config(priv);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
/* Disable IDIV for this port */
|
|
rc = sja1105_cgu_idiv_config(priv, port, false, 1);
|
|
if (rc < 0)
|
|
return rc;
|
|
/* Source to sink mappings */
|
|
rc = sja1105_cgu_rmii_ref_clk_config(priv, port);
|
|
if (rc < 0)
|
|
return rc;
|
|
if (role == XMII_MAC) {
|
|
rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int sja1105_clocking_setup_port(struct sja1105_private *priv, int port)
|
|
{
|
|
struct sja1105_xmii_params_entry *mii;
|
|
struct device *dev = priv->ds->dev;
|
|
sja1105_phy_interface_t phy_mode;
|
|
sja1105_mii_role_t role;
|
|
int rc;
|
|
|
|
mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
|
|
|
|
/* RGMII etc */
|
|
phy_mode = mii->xmii_mode[port];
|
|
/* MAC or PHY, for applicable types (not RGMII) */
|
|
role = mii->phy_mac[port];
|
|
|
|
switch (phy_mode) {
|
|
case XMII_MODE_MII:
|
|
rc = sja1105_mii_clocking_setup(priv, port, role);
|
|
break;
|
|
case XMII_MODE_RMII:
|
|
rc = sja1105_rmii_clocking_setup(priv, port, role);
|
|
break;
|
|
case XMII_MODE_RGMII:
|
|
rc = sja1105_rgmii_clocking_setup(priv, port, role);
|
|
break;
|
|
default:
|
|
dev_err(dev, "Invalid interface mode specified: %d\n",
|
|
phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
if (rc)
|
|
dev_err(dev, "Clocking setup for port %d failed: %d\n",
|
|
port, rc);
|
|
return rc;
|
|
}
|
|
|
|
int sja1105_clocking_setup(struct sja1105_private *priv)
|
|
{
|
|
int port, rc;
|
|
|
|
for (port = 0; port < SJA1105_NUM_PORTS; port++) {
|
|
rc = sja1105_clocking_setup_port(priv, port);
|
|
if (rc < 0)
|
|
return rc;
|
|
}
|
|
return 0;
|
|
}
|