132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/*
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MTHCA_WQE_H
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#define MTHCA_WQE_H
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#include <linux/types.h>
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enum {
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MTHCA_NEXT_DBD = 1 << 7,
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MTHCA_NEXT_FENCE = 1 << 6,
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MTHCA_NEXT_CQ_UPDATE = 1 << 3,
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MTHCA_NEXT_EVENT_GEN = 1 << 2,
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MTHCA_NEXT_SOLICIT = 1 << 1,
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MTHCA_NEXT_IP_CSUM = 1 << 4,
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MTHCA_NEXT_TCP_UDP_CSUM = 1 << 5,
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MTHCA_MLX_VL15 = 1 << 17,
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MTHCA_MLX_SLR = 1 << 16
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};
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enum {
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MTHCA_INVAL_LKEY = 0x100,
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MTHCA_TAVOR_MAX_WQES_PER_RECV_DB = 256,
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MTHCA_ARBEL_MAX_WQES_PER_SEND_DB = 255
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};
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struct mthca_next_seg {
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__be32 nda_op; /* [31:6] next WQE [4:0] next opcode */
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__be32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */
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__be32 flags; /* [3] CQ [2] Event [1] Solicit */
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__be32 imm; /* immediate data */
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};
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struct mthca_tavor_ud_seg {
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u32 reserved1;
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__be32 lkey;
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__be64 av_addr;
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u32 reserved2[4];
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__be32 dqpn;
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__be32 qkey;
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u32 reserved3[2];
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};
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struct mthca_arbel_ud_seg {
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__be32 av[8];
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__be32 dqpn;
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__be32 qkey;
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u32 reserved[2];
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};
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struct mthca_bind_seg {
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__be32 flags; /* [31] Atomic [30] rem write [29] rem read */
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u32 reserved;
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__be32 new_rkey;
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__be32 lkey;
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__be64 addr;
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__be64 length;
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};
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struct mthca_raddr_seg {
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__be64 raddr;
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__be32 rkey;
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u32 reserved;
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};
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struct mthca_atomic_seg {
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__be64 swap_add;
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__be64 compare;
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};
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struct mthca_data_seg {
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__be32 byte_count;
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__be32 lkey;
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__be64 addr;
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};
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struct mthca_mlx_seg {
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__be32 nda_op;
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__be32 nds;
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__be32 flags; /* [17] VL15 [16] SLR [14:12] static rate
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[11:8] SL [3] C [2] E */
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__be16 rlid;
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__be16 vcrc;
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};
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static __always_inline void mthca_set_data_seg(struct mthca_data_seg *dseg,
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struct ib_sge *sg)
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{
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dseg->byte_count = cpu_to_be32(sg->length);
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dseg->lkey = cpu_to_be32(sg->lkey);
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dseg->addr = cpu_to_be64(sg->addr);
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}
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static __always_inline void mthca_set_data_seg_inval(struct mthca_data_seg *dseg)
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{
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dseg->byte_count = 0;
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dseg->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
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dseg->addr = 0;
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}
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#endif /* MTHCA_WQE_H */
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