144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
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*/
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#ifndef _EFA_COM_H_
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#define _EFA_COM_H_
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/semaphore.h>
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#include <linux/sched.h>
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#include <rdma/ib_verbs.h>
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#include "efa_common_defs.h"
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#include "efa_admin_defs.h"
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#include "efa_admin_cmds_defs.h"
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#include "efa_regs_defs.h"
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#define EFA_MAX_HANDLERS 256
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struct efa_com_admin_cq {
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struct efa_admin_acq_entry *entries;
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dma_addr_t dma_addr;
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spinlock_t lock; /* Protects ACQ */
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u16 cc; /* consumer counter */
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u8 phase;
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};
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struct efa_com_admin_sq {
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struct efa_admin_aq_entry *entries;
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dma_addr_t dma_addr;
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spinlock_t lock; /* Protects ASQ */
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u32 __iomem *db_addr;
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u16 cc; /* consumer counter */
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u16 pc; /* producer counter */
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u8 phase;
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};
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/* Don't use anything other than atomic64 */
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struct efa_com_stats_admin {
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atomic64_t submitted_cmd;
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atomic64_t completed_cmd;
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atomic64_t no_completion;
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};
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enum {
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EFA_AQ_STATE_RUNNING_BIT = 0,
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EFA_AQ_STATE_POLLING_BIT = 1,
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};
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struct efa_com_admin_queue {
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void *dmadev;
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void *efa_dev;
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struct efa_comp_ctx *comp_ctx;
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u32 completion_timeout; /* usecs */
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u16 poll_interval; /* msecs */
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u16 depth;
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struct efa_com_admin_cq cq;
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struct efa_com_admin_sq sq;
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u16 msix_vector_idx;
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unsigned long state;
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/* Count the number of available admin commands */
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struct semaphore avail_cmds;
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struct efa_com_stats_admin stats;
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spinlock_t comp_ctx_lock; /* Protects completion context pool */
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u32 *comp_ctx_pool;
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u16 comp_ctx_pool_next;
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};
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struct efa_aenq_handlers;
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struct efa_com_aenq {
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struct efa_admin_aenq_entry *entries;
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struct efa_aenq_handlers *aenq_handlers;
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dma_addr_t dma_addr;
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u32 cc; /* consumer counter */
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u16 msix_vector_idx;
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u16 depth;
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u8 phase;
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};
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struct efa_com_mmio_read {
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struct efa_admin_mmio_req_read_less_resp *read_resp;
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dma_addr_t read_resp_dma_addr;
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u16 seq_num;
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u16 mmio_read_timeout; /* usecs */
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/* serializes mmio reads */
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spinlock_t lock;
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};
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struct efa_com_dev {
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struct efa_com_admin_queue aq;
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struct efa_com_aenq aenq;
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u8 __iomem *reg_bar;
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void *dmadev;
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void *efa_dev;
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u32 supported_features;
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u32 dma_addr_bits;
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struct efa_com_mmio_read mmio_read;
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};
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typedef void (*efa_aenq_handler)(void *data,
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struct efa_admin_aenq_entry *aenq_e);
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/* Holds aenq handlers. Indexed by AENQ event group */
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struct efa_aenq_handlers {
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efa_aenq_handler handlers[EFA_MAX_HANDLERS];
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efa_aenq_handler unimplemented_handler;
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};
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int efa_com_admin_init(struct efa_com_dev *edev,
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struct efa_aenq_handlers *aenq_handlers);
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void efa_com_admin_destroy(struct efa_com_dev *edev);
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int efa_com_dev_reset(struct efa_com_dev *edev,
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enum efa_regs_reset_reason_types reset_reason);
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void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling);
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void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev);
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int efa_com_mmio_reg_read_init(struct efa_com_dev *edev);
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void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev);
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int efa_com_validate_version(struct efa_com_dev *edev);
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int efa_com_get_dma_width(struct efa_com_dev *edev);
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int efa_com_cmd_exec(struct efa_com_admin_queue *aq,
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struct efa_admin_aq_entry *cmd,
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size_t cmd_size,
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struct efa_admin_acq_entry *comp,
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size_t comp_size);
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void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data);
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#endif /* _EFA_COM_H_ */
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