459 lines
13 KiB
C
459 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Extcon charger detection driver for Intel Cherrytrail Whiskey Cove PMIC
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* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
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* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
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*/
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#include <linux/extcon-provider.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include "extcon-intel.h"
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#define CHT_WC_PHYCTRL 0x5e07
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#define CHT_WC_CHGRCTRL0 0x5e16
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#define CHT_WC_CHGRCTRL0_CHGRRESET BIT(0)
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#define CHT_WC_CHGRCTRL0_EMRGCHREN BIT(1)
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#define CHT_WC_CHGRCTRL0_EXTCHRDIS BIT(2)
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#define CHT_WC_CHGRCTRL0_SWCONTROL BIT(3)
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#define CHT_WC_CHGRCTRL0_TTLCK BIT(4)
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#define CHT_WC_CHGRCTRL0_CCSM_OFF BIT(5)
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#define CHT_WC_CHGRCTRL0_DBPOFF BIT(6)
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#define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK BIT(7)
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#define CHT_WC_CHGRCTRL1 0x5e17
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#define CHT_WC_CHGRCTRL1_FUSB_INLMT_100 BIT(0)
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#define CHT_WC_CHGRCTRL1_FUSB_INLMT_150 BIT(1)
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#define CHT_WC_CHGRCTRL1_FUSB_INLMT_500 BIT(2)
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#define CHT_WC_CHGRCTRL1_FUSB_INLMT_900 BIT(3)
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#define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500 BIT(4)
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#define CHT_WC_CHGRCTRL1_FTEMP_EVENT BIT(5)
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#define CHT_WC_CHGRCTRL1_OTGMODE BIT(6)
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#define CHT_WC_CHGRCTRL1_DBPEN BIT(7)
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#define CHT_WC_USBSRC 0x5e29
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#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
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#define CHT_WC_USBSRC_STS_SUCCESS 2
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#define CHT_WC_USBSRC_STS_FAIL 3
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#define CHT_WC_USBSRC_TYPE_SHIFT 2
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#define CHT_WC_USBSRC_TYPE_MASK GENMASK(5, 2)
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#define CHT_WC_USBSRC_TYPE_NONE 0
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#define CHT_WC_USBSRC_TYPE_SDP 1
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#define CHT_WC_USBSRC_TYPE_DCP 2
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#define CHT_WC_USBSRC_TYPE_CDP 3
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#define CHT_WC_USBSRC_TYPE_ACA 4
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#define CHT_WC_USBSRC_TYPE_SE1 5
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#define CHT_WC_USBSRC_TYPE_MHL 6
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#define CHT_WC_USBSRC_TYPE_FLOATING 7
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#define CHT_WC_USBSRC_TYPE_OTHER 8
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#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
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#define CHT_WC_CHGDISCTRL 0x5e2f
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#define CHT_WC_CHGDISCTRL_OUT BIT(0)
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/* 0 - open drain, 1 - regular push-pull output */
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#define CHT_WC_CHGDISCTRL_DRV BIT(4)
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/* 0 - pin is controlled by SW, 1 - by HW */
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#define CHT_WC_CHGDISCTRL_FN BIT(6)
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#define CHT_WC_PWRSRC_IRQ 0x6e03
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#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
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#define CHT_WC_PWRSRC_STS 0x6e1e
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#define CHT_WC_PWRSRC_VBUS BIT(0)
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#define CHT_WC_PWRSRC_DC BIT(1)
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#define CHT_WC_PWRSRC_BATT BIT(2)
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#define CHT_WC_PWRSRC_USBID_MASK GENMASK(4, 3)
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#define CHT_WC_PWRSRC_USBID_SHIFT 3
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#define CHT_WC_PWRSRC_RID_ACA 0
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#define CHT_WC_PWRSRC_RID_GND 1
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#define CHT_WC_PWRSRC_RID_FLOAT 2
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#define CHT_WC_VBUS_GPIO_CTLO 0x6e2d
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#define CHT_WC_VBUS_GPIO_CTLO_OUTPUT BIT(0)
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#define CHT_WC_VBUS_GPIO_CTLO_DRV_OD BIT(4)
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#define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT BIT(5)
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enum cht_wc_mux_select {
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MUX_SEL_PMIC = 0,
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MUX_SEL_SOC,
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};
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static const unsigned int cht_wc_extcon_cables[] = {
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EXTCON_USB,
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EXTCON_USB_HOST,
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EXTCON_CHG_USB_SDP,
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EXTCON_CHG_USB_CDP,
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EXTCON_CHG_USB_DCP,
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EXTCON_CHG_USB_ACA,
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EXTCON_NONE,
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};
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struct cht_wc_extcon_data {
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struct device *dev;
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struct regmap *regmap;
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struct extcon_dev *edev;
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unsigned int previous_cable;
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bool usb_host;
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};
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static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
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{
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switch ((pwrsrc_sts & CHT_WC_PWRSRC_USBID_MASK) >> CHT_WC_PWRSRC_USBID_SHIFT) {
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case CHT_WC_PWRSRC_RID_GND:
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return INTEL_USB_ID_GND;
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case CHT_WC_PWRSRC_RID_FLOAT:
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return INTEL_USB_ID_FLOAT;
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case CHT_WC_PWRSRC_RID_ACA:
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default:
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/*
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* Once we have IIO support for the GPADC we should read
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* the USBID GPADC channel here and determine ACA role
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* based on that.
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*/
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return INTEL_USB_ID_FLOAT;
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}
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}
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static int cht_wc_extcon_get_charger(struct cht_wc_extcon_data *ext,
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bool ignore_errors)
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{
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int ret, usbsrc, status;
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unsigned long timeout;
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/* Charger detection can take upto 600ms, wait 800ms max. */
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timeout = jiffies + msecs_to_jiffies(800);
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do {
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ret = regmap_read(ext->regmap, CHT_WC_USBSRC, &usbsrc);
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if (ret) {
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dev_err(ext->dev, "Error reading usbsrc: %d\n", ret);
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return ret;
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}
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status = usbsrc & CHT_WC_USBSRC_STS_MASK;
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if (status == CHT_WC_USBSRC_STS_SUCCESS ||
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status == CHT_WC_USBSRC_STS_FAIL)
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break;
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msleep(50); /* Wait a bit before retrying */
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} while (time_before(jiffies, timeout));
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if (status != CHT_WC_USBSRC_STS_SUCCESS) {
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if (ignore_errors)
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return EXTCON_CHG_USB_SDP; /* Save fallback */
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if (status == CHT_WC_USBSRC_STS_FAIL)
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dev_warn(ext->dev, "Could not detect charger type\n");
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else
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dev_warn(ext->dev, "Timeout detecting charger type\n");
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return EXTCON_CHG_USB_SDP; /* Save fallback */
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}
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usbsrc = (usbsrc & CHT_WC_USBSRC_TYPE_MASK) >> CHT_WC_USBSRC_TYPE_SHIFT;
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switch (usbsrc) {
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default:
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dev_warn(ext->dev,
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"Unhandled charger type %d, defaulting to SDP\n",
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ret);
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return EXTCON_CHG_USB_SDP;
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case CHT_WC_USBSRC_TYPE_SDP:
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case CHT_WC_USBSRC_TYPE_FLOATING:
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case CHT_WC_USBSRC_TYPE_OTHER:
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return EXTCON_CHG_USB_SDP;
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case CHT_WC_USBSRC_TYPE_CDP:
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return EXTCON_CHG_USB_CDP;
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case CHT_WC_USBSRC_TYPE_DCP:
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case CHT_WC_USBSRC_TYPE_DCP_EXTPHY:
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case CHT_WC_USBSRC_TYPE_MHL: /* MHL2+ delivers upto 2A, treat as DCP */
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return EXTCON_CHG_USB_DCP;
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case CHT_WC_USBSRC_TYPE_ACA:
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return EXTCON_CHG_USB_ACA;
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}
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}
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static void cht_wc_extcon_set_phymux(struct cht_wc_extcon_data *ext, u8 state)
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{
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int ret;
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ret = regmap_write(ext->regmap, CHT_WC_PHYCTRL, state);
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if (ret)
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dev_err(ext->dev, "Error writing phyctrl: %d\n", ret);
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}
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static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
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bool enable)
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{
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int ret, val;
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/*
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* The 5V boost converter is enabled through a gpio on the PMIC, since
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* there currently is no gpio driver we access the gpio reg directly.
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*/
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val = CHT_WC_VBUS_GPIO_CTLO_DRV_OD | CHT_WC_VBUS_GPIO_CTLO_DIR_OUT;
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if (enable)
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val |= CHT_WC_VBUS_GPIO_CTLO_OUTPUT;
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ret = regmap_write(ext->regmap, CHT_WC_VBUS_GPIO_CTLO, val);
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if (ret)
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dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
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}
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static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
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bool enable)
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{
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unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0;
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int ret;
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ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL1,
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CHT_WC_CHGRCTRL1_OTGMODE, val);
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if (ret)
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dev_err(ext->dev, "Error updating CHGRCTRL1 reg: %d\n", ret);
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}
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static void cht_wc_extcon_enable_charging(struct cht_wc_extcon_data *ext,
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bool enable)
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{
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unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT;
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int ret;
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ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
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CHT_WC_CHGDISCTRL_OUT, val);
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if (ret)
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dev_err(ext->dev, "Error updating CHGDISCTRL reg: %d\n", ret);
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}
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/* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
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static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
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unsigned int cable, bool state)
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{
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extcon_set_state_sync(ext->edev, cable, state);
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if (cable == EXTCON_CHG_USB_SDP)
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extcon_set_state_sync(ext->edev, EXTCON_USB, state);
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}
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static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
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{
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int ret, pwrsrc_sts, id;
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unsigned int cable = EXTCON_NONE;
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/* Ignore errors in host mode, as the 5v boost converter is on then */
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bool ignore_get_charger_errors = ext->usb_host;
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ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
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if (ret) {
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dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
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return;
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}
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id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
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if (id == INTEL_USB_ID_GND) {
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cht_wc_extcon_enable_charging(ext, false);
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cht_wc_extcon_set_otgmode(ext, true);
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/* The 5v boost causes a false VBUS / SDP detect, skip */
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goto charger_det_done;
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}
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cht_wc_extcon_set_otgmode(ext, false);
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cht_wc_extcon_enable_charging(ext, true);
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/* Plugged into a host/charger or not connected? */
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if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
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/* Route D+ and D- to PMIC for future charger detection */
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cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
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goto set_state;
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}
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ret = cht_wc_extcon_get_charger(ext, ignore_get_charger_errors);
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if (ret >= 0)
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cable = ret;
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charger_det_done:
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/* Route D+ and D- to SoC for the host or gadget controller */
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cht_wc_extcon_set_phymux(ext, MUX_SEL_SOC);
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set_state:
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if (cable != ext->previous_cable) {
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cht_wc_extcon_set_state(ext, cable, true);
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cht_wc_extcon_set_state(ext, ext->previous_cable, false);
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ext->previous_cable = cable;
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}
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ext->usb_host = ((id == INTEL_USB_ID_GND) || (id == INTEL_USB_RID_A));
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extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
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}
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static irqreturn_t cht_wc_extcon_isr(int irq, void *data)
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{
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struct cht_wc_extcon_data *ext = data;
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int ret, irqs;
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ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_IRQ, &irqs);
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if (ret) {
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dev_err(ext->dev, "Error reading irqs: %d\n", ret);
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return IRQ_NONE;
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}
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cht_wc_extcon_pwrsrc_event(ext);
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ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ, irqs);
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if (ret) {
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dev_err(ext->dev, "Error writing irqs: %d\n", ret);
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return IRQ_NONE;
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}
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return IRQ_HANDLED;
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}
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static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
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{
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int ret, mask, val;
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val = enable ? 0 : CHT_WC_CHGDISCTRL_FN;
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ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
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CHT_WC_CHGDISCTRL_FN, val);
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if (ret)
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dev_err(ext->dev,
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"Error setting sw control for CHGDIS pin: %d\n",
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ret);
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mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF;
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val = enable ? mask : 0;
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ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
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if (ret)
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dev_err(ext->dev, "Error setting sw control: %d\n", ret);
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return ret;
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}
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static int cht_wc_extcon_probe(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
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struct cht_wc_extcon_data *ext;
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unsigned long mask = ~(CHT_WC_PWRSRC_VBUS | CHT_WC_PWRSRC_USBID_MASK);
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int pwrsrc_sts, id;
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int irq, ret;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ext = devm_kzalloc(&pdev->dev, sizeof(*ext), GFP_KERNEL);
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if (!ext)
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return -ENOMEM;
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ext->dev = &pdev->dev;
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ext->regmap = pmic->regmap;
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ext->previous_cable = EXTCON_NONE;
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/* Initialize extcon device */
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ext->edev = devm_extcon_dev_allocate(ext->dev, cht_wc_extcon_cables);
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if (IS_ERR(ext->edev))
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return PTR_ERR(ext->edev);
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/*
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* When a host-cable is detected the BIOS enables an external 5v boost
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* converter to power connected devices there are 2 problems with this:
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* 1) This gets seen by the external battery charger as a valid Vbus
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* supply and it then tries to feed Vsys from this creating a
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* feedback loop which causes aprox. 300 mA extra battery drain
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* (and unless we drive the external-charger-disable pin high it
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* also tries to charge the battery causing even more feedback).
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* 2) This gets seen by the pwrsrc block as a SDP USB Vbus supply
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* Since the external battery charger has its own 5v boost converter
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* which does not have these issues, we simply turn the separate
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* external 5v boost converter off and leave it off entirely.
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*/
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cht_wc_extcon_set_5v_boost(ext, false);
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/* Enable sw control */
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ret = cht_wc_extcon_sw_control(ext, true);
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if (ret)
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goto disable_sw_control;
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/* Disable charging by external battery charger */
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cht_wc_extcon_enable_charging(ext, false);
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/* Register extcon device */
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ret = devm_extcon_dev_register(ext->dev, ext->edev);
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if (ret) {
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dev_err(ext->dev, "Error registering extcon device: %d\n", ret);
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goto disable_sw_control;
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}
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ret = regmap_read(ext->regmap, CHT_WC_PWRSRC_STS, &pwrsrc_sts);
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if (ret) {
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dev_err(ext->dev, "Error reading pwrsrc status: %d\n", ret);
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goto disable_sw_control;
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}
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/*
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* If no USB host or device connected, route D+ and D- to PMIC for
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* initial charger detection
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*/
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id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
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if (id != INTEL_USB_ID_GND)
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cht_wc_extcon_set_phymux(ext, MUX_SEL_PMIC);
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/* Get initial state */
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cht_wc_extcon_pwrsrc_event(ext);
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ret = devm_request_threaded_irq(ext->dev, irq, NULL, cht_wc_extcon_isr,
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IRQF_ONESHOT, pdev->name, ext);
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if (ret) {
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dev_err(ext->dev, "Error requesting interrupt: %d\n", ret);
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goto disable_sw_control;
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}
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/* Unmask irqs */
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ret = regmap_write(ext->regmap, CHT_WC_PWRSRC_IRQ_MASK, mask);
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if (ret) {
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dev_err(ext->dev, "Error writing irq-mask: %d\n", ret);
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goto disable_sw_control;
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}
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platform_set_drvdata(pdev, ext);
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return 0;
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disable_sw_control:
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cht_wc_extcon_sw_control(ext, false);
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return ret;
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}
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static int cht_wc_extcon_remove(struct platform_device *pdev)
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{
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struct cht_wc_extcon_data *ext = platform_get_drvdata(pdev);
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cht_wc_extcon_sw_control(ext, false);
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return 0;
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}
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static const struct platform_device_id cht_wc_extcon_table[] = {
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{ .name = "cht_wcove_pwrsrc" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, cht_wc_extcon_table);
|
|
|
|
static struct platform_driver cht_wc_extcon_driver = {
|
|
.probe = cht_wc_extcon_probe,
|
|
.remove = cht_wc_extcon_remove,
|
|
.id_table = cht_wc_extcon_table,
|
|
.driver = {
|
|
.name = "cht_wcove_pwrsrc",
|
|
},
|
|
};
|
|
module_platform_driver(cht_wc_extcon_driver);
|
|
|
|
MODULE_DESCRIPTION("Intel Cherrytrail Whiskey Cove PMIC extcon driver");
|
|
MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
|
|
MODULE_LICENSE("GPL v2");
|