392 lines
9.8 KiB
C
392 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2018 Intel Corporation. All rights reserved. */
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#include <linux/libnvdimm.h>
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#include <linux/ndctl.h>
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#include <linux/acpi.h>
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#include <asm/smp.h>
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#include "intel.h"
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#include "nfit.h"
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static unsigned long intel_security_flags(struct nvdimm *nvdimm,
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enum nvdimm_passphrase_type ptype)
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{
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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unsigned long security_flags = 0;
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_get_security_state cmd;
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} nd_cmd = {
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.pkg = {
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.nd_command = NVDIMM_INTEL_GET_SECURITY_STATE,
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_out =
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sizeof(struct nd_intel_get_security_state),
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.nd_fw_size =
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sizeof(struct nd_intel_get_security_state),
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},
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};
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int rc;
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if (!test_bit(NVDIMM_INTEL_GET_SECURITY_STATE, &nfit_mem->dsm_mask))
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return 0;
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/*
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* Short circuit the state retrieval while we are doing overwrite.
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* The DSM spec states that the security state is indeterminate
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* until the overwrite DSM completes.
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*/
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if (nvdimm_in_overwrite(nvdimm) && ptype == NVDIMM_USER)
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return BIT(NVDIMM_SECURITY_OVERWRITE);
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0 || nd_cmd.cmd.status) {
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pr_err("%s: security state retrieval failed (%d:%#x)\n",
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nvdimm_name(nvdimm), rc, nd_cmd.cmd.status);
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return 0;
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}
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/* check and see if security is enabled and locked */
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if (ptype == NVDIMM_MASTER) {
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if (nd_cmd.cmd.extended_state & ND_INTEL_SEC_ESTATE_ENABLED)
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set_bit(NVDIMM_SECURITY_UNLOCKED, &security_flags);
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else
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set_bit(NVDIMM_SECURITY_DISABLED, &security_flags);
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if (nd_cmd.cmd.extended_state & ND_INTEL_SEC_ESTATE_PLIMIT)
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set_bit(NVDIMM_SECURITY_FROZEN, &security_flags);
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return security_flags;
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}
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_UNSUPPORTED)
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return 0;
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_ENABLED) {
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_FROZEN ||
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nd_cmd.cmd.state & ND_INTEL_SEC_STATE_PLIMIT)
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set_bit(NVDIMM_SECURITY_FROZEN, &security_flags);
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if (nd_cmd.cmd.state & ND_INTEL_SEC_STATE_LOCKED)
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set_bit(NVDIMM_SECURITY_LOCKED, &security_flags);
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else
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set_bit(NVDIMM_SECURITY_UNLOCKED, &security_flags);
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} else
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set_bit(NVDIMM_SECURITY_DISABLED, &security_flags);
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return security_flags;
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}
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static int intel_security_freeze(struct nvdimm *nvdimm)
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{
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_freeze_lock cmd;
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} nd_cmd = {
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.pkg = {
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.nd_command = NVDIMM_INTEL_FREEZE_LOCK,
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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},
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};
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int rc;
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if (!test_bit(NVDIMM_INTEL_FREEZE_LOCK, &nfit_mem->dsm_mask))
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return -ENOTTY;
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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if (nd_cmd.cmd.status)
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return -EIO;
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return 0;
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}
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static int intel_security_change_key(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *old_data,
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const struct nvdimm_key_data *new_data,
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enum nvdimm_passphrase_type ptype)
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{
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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unsigned int cmd = ptype == NVDIMM_MASTER ?
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NVDIMM_INTEL_SET_MASTER_PASSPHRASE :
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NVDIMM_INTEL_SET_PASSPHRASE;
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_set_passphrase cmd;
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} nd_cmd = {
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.pkg = {
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE * 2,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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.nd_command = cmd,
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},
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};
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int rc;
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if (!test_bit(cmd, &nfit_mem->dsm_mask))
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return -ENOTTY;
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memcpy(nd_cmd.cmd.old_pass, old_data->data,
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sizeof(nd_cmd.cmd.old_pass));
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memcpy(nd_cmd.cmd.new_pass, new_data->data,
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sizeof(nd_cmd.cmd.new_pass));
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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switch (nd_cmd.cmd.status) {
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case 0:
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return 0;
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case ND_INTEL_STATUS_INVALID_PASS:
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return -EINVAL;
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case ND_INTEL_STATUS_NOT_SUPPORTED:
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return -EOPNOTSUPP;
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case ND_INTEL_STATUS_INVALID_STATE:
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default:
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return -EIO;
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}
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}
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static void nvdimm_invalidate_cache(void);
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static int __maybe_unused intel_security_unlock(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key_data)
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{
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_unlock_unit cmd;
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} nd_cmd = {
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.pkg = {
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.nd_command = NVDIMM_INTEL_UNLOCK_UNIT,
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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},
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};
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int rc;
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if (!test_bit(NVDIMM_INTEL_UNLOCK_UNIT, &nfit_mem->dsm_mask))
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return -ENOTTY;
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memcpy(nd_cmd.cmd.passphrase, key_data->data,
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sizeof(nd_cmd.cmd.passphrase));
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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switch (nd_cmd.cmd.status) {
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case 0:
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break;
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case ND_INTEL_STATUS_INVALID_PASS:
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return -EINVAL;
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default:
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return -EIO;
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}
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/* DIMM unlocked, invalidate all CPU caches before we read it */
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nvdimm_invalidate_cache();
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return 0;
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}
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static int intel_security_disable(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key_data)
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{
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int rc;
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_disable_passphrase cmd;
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} nd_cmd = {
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.pkg = {
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.nd_command = NVDIMM_INTEL_DISABLE_PASSPHRASE,
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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},
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};
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if (!test_bit(NVDIMM_INTEL_DISABLE_PASSPHRASE, &nfit_mem->dsm_mask))
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return -ENOTTY;
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memcpy(nd_cmd.cmd.passphrase, key_data->data,
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sizeof(nd_cmd.cmd.passphrase));
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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switch (nd_cmd.cmd.status) {
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case 0:
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break;
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case ND_INTEL_STATUS_INVALID_PASS:
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return -EINVAL;
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case ND_INTEL_STATUS_INVALID_STATE:
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default:
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return -ENXIO;
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}
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return 0;
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}
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static int __maybe_unused intel_security_erase(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *key,
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enum nvdimm_passphrase_type ptype)
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{
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int rc;
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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unsigned int cmd = ptype == NVDIMM_MASTER ?
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NVDIMM_INTEL_MASTER_SECURE_ERASE : NVDIMM_INTEL_SECURE_ERASE;
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_secure_erase cmd;
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} nd_cmd = {
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.pkg = {
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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.nd_command = cmd,
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},
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};
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if (!test_bit(cmd, &nfit_mem->dsm_mask))
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return -ENOTTY;
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/* flush all cache before we erase DIMM */
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nvdimm_invalidate_cache();
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memcpy(nd_cmd.cmd.passphrase, key->data,
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sizeof(nd_cmd.cmd.passphrase));
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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switch (nd_cmd.cmd.status) {
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case 0:
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break;
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case ND_INTEL_STATUS_NOT_SUPPORTED:
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return -EOPNOTSUPP;
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case ND_INTEL_STATUS_INVALID_PASS:
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return -EINVAL;
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case ND_INTEL_STATUS_INVALID_STATE:
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default:
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return -ENXIO;
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}
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/* DIMM erased, invalidate all CPU caches before we read it */
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nvdimm_invalidate_cache();
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return 0;
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}
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static int __maybe_unused intel_security_query_overwrite(struct nvdimm *nvdimm)
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{
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int rc;
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_query_overwrite cmd;
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} nd_cmd = {
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.pkg = {
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.nd_command = NVDIMM_INTEL_QUERY_OVERWRITE,
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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},
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};
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if (!test_bit(NVDIMM_INTEL_QUERY_OVERWRITE, &nfit_mem->dsm_mask))
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return -ENOTTY;
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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switch (nd_cmd.cmd.status) {
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case 0:
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break;
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case ND_INTEL_STATUS_OQUERY_INPROGRESS:
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return -EBUSY;
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default:
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return -ENXIO;
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}
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/* flush all cache before we make the nvdimms available */
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nvdimm_invalidate_cache();
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return 0;
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}
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static int __maybe_unused intel_security_overwrite(struct nvdimm *nvdimm,
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const struct nvdimm_key_data *nkey)
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{
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int rc;
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struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
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struct {
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struct nd_cmd_pkg pkg;
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struct nd_intel_overwrite cmd;
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} nd_cmd = {
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.pkg = {
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.nd_command = NVDIMM_INTEL_OVERWRITE,
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.nd_family = NVDIMM_FAMILY_INTEL,
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.nd_size_in = ND_INTEL_PASSPHRASE_SIZE,
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.nd_size_out = ND_INTEL_STATUS_SIZE,
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.nd_fw_size = ND_INTEL_STATUS_SIZE,
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},
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};
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if (!test_bit(NVDIMM_INTEL_OVERWRITE, &nfit_mem->dsm_mask))
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return -ENOTTY;
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/* flush all cache before we erase DIMM */
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nvdimm_invalidate_cache();
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memcpy(nd_cmd.cmd.passphrase, nkey->data,
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sizeof(nd_cmd.cmd.passphrase));
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rc = nvdimm_ctl(nvdimm, ND_CMD_CALL, &nd_cmd, sizeof(nd_cmd), NULL);
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if (rc < 0)
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return rc;
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switch (nd_cmd.cmd.status) {
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case 0:
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return 0;
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case ND_INTEL_STATUS_OVERWRITE_UNSUPPORTED:
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return -ENOTSUPP;
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case ND_INTEL_STATUS_INVALID_PASS:
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return -EINVAL;
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case ND_INTEL_STATUS_INVALID_STATE:
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default:
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return -ENXIO;
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}
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}
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/*
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* TODO: define a cross arch wbinvd equivalent when/if
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* NVDIMM_FAMILY_INTEL command support arrives on another arch.
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*/
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#ifdef CONFIG_X86
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static void nvdimm_invalidate_cache(void)
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{
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wbinvd_on_all_cpus();
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}
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#else
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static void nvdimm_invalidate_cache(void)
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{
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WARN_ON_ONCE("cache invalidation required after unlock\n");
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}
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#endif
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static const struct nvdimm_security_ops __intel_security_ops = {
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.get_flags = intel_security_flags,
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.freeze = intel_security_freeze,
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.change_key = intel_security_change_key,
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.disable = intel_security_disable,
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#ifdef CONFIG_X86
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.unlock = intel_security_unlock,
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.erase = intel_security_erase,
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.overwrite = intel_security_overwrite,
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.query_overwrite = intel_security_query_overwrite,
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#endif
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};
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const struct nvdimm_security_ops *intel_security_ops = &__intel_security_ops;
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