804 lines
21 KiB
C
804 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Various workarounds for chipset bugs.
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This code runs very early and can't use the regular PCI subsystem
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The entries are keyed to PCI bridges which usually identify chipsets
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uniquely.
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This is only for whole classes of chipsets with specific problems which
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need early invasive action (e.g. before the timers are initialized).
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Most PCI device specific workarounds can be done later and should be
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in standard PCI quirks
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Mainboard specific bugs should be handled by DMI entries.
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CPU specific bugs in setup.c */
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/pci_ids.h>
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#include <linux/bcma/bcma.h>
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#include <linux/bcma/bcma_regs.h>
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#include <linux/platform_data/x86/apple.h>
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#include <drm/i915_drm.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/io_apic.h>
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#include <asm/apic.h>
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#include <asm/hpet.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/irq_remapping.h>
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#include <asm/early_ioremap.h>
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static void __init fix_hypertransport_config(int num, int slot, int func)
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{
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u32 htcfg;
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/*
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* we found a hypertransport bus
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* make sure that we are broadcasting
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* interrupts to all cpus on the ht bus
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* if we're using extended apic ids
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*/
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htcfg = read_pci_config(num, slot, func, 0x68);
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if (htcfg & (1 << 18)) {
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printk(KERN_INFO "Detected use of extended apic ids "
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"on hypertransport bus\n");
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if ((htcfg & (1 << 17)) == 0) {
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printk(KERN_INFO "Enabling hypertransport extended "
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"apic interrupt broadcast\n");
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printk(KERN_INFO "Note this is a bios bug, "
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"please contact your hw vendor\n");
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htcfg |= (1 << 17);
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write_pci_config(num, slot, func, 0x68, htcfg);
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}
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}
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}
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static void __init via_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_GART_IOMMU
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if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
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!gart_iommu_aperture_allowed) {
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printk(KERN_INFO
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"Looks like a VIA chipset. Disabling IOMMU."
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" Override with iommu=allowed\n");
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gart_iommu_aperture_disabled = 1;
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}
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#endif
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}
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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static int __init nvidia_hpet_check(struct acpi_table_header *header)
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{
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return 0;
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}
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#endif /* CONFIG_X86_IO_APIC */
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#endif /* CONFIG_ACPI */
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static void __init nvidia_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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/*
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* Only applies to Nvidia root ports (bus 0) and not to
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* Nvidia graphics cards with PCI ports on secondary buses.
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*/
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if (num)
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return;
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/*
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* All timer overrides on Nvidia are
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* wrong unless HPET is enabled.
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* Unfortunately that's not true on many Asus boards.
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* We don't know yet how to detect this automatically, but
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* at least allow a command line override.
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*/
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if (acpi_use_timer_override)
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return;
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if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
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acpi_skip_timer_override = 1;
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printk(KERN_INFO "Nvidia board "
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"detected. Ignoring ACPI "
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"timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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#endif
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#endif
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/* RED-PEN skip them on mptables too? */
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
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static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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b = read_pci_config_byte(num, slot, func, 0xac);
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b &= ~(1<<5);
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write_pci_config_byte(num, slot, func, 0xac, b);
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d = read_pci_config(num, slot, func, 0x70);
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d |= 1<<8;
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write_pci_config(num, slot, func, 0x70, d);
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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if (acpi_use_timer_override)
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return;
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d = ati_ixp4x0_rev(num, slot, func);
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if (d < 0x82)
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acpi_skip_timer_override = 1;
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else {
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/* check for IRQ0 interrupt swap */
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outb(0x72, 0xcd6); b = inb(0xcd7);
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if (!(b & 0x2))
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acpi_skip_timer_override = 1;
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}
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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static u32 __init ati_sbx00_rev(int num, int slot, int func)
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{
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u32 d;
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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u32 d, rev;
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rev = ati_sbx00_rev(num, slot, func);
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if (rev >= 0x40)
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acpi_fix_pin2_polarity = 1;
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/*
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* SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
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* SB700: revisions 0x39, 0x3a, ...
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* SB800: revisions 0x40, 0x41, ...
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*/
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if (rev >= 0x39)
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return;
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if (acpi_use_timer_override)
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return;
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/* check for IRQ0 interrupt swap */
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d = read_pci_config(num, slot, func, 0x64);
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if (!(d & (1<<14)))
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acpi_skip_timer_override = 1;
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB600 revision 0x%x\n", rev);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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#else
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static void __init ati_bugs(int num, int slot, int func)
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{
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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}
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#endif
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static void __init intel_remapping_check(int num, int slot, int func)
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{
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u8 revision;
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u16 device;
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
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/*
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* Revision <= 13 of all triggering devices id in this quirk
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* have a problem draining interrupts when irq remapping is
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* enabled, and should be flagged as broken. Additionally
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* revision 0x22 of device id 0x3405 has this problem.
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*/
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if (revision <= 0x13)
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set_irq_remapping_broken();
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else if (device == 0x3405 && revision == 0x22)
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set_irq_remapping_broken();
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}
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/*
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* Systems with Intel graphics controllers set aside memory exclusively
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* for gfx driver use. This memory is not marked in the E820 as reserved
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* or as RAM, and so is subject to overlap from E820 manipulation later
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* in the boot process. On some systems, MMIO space is allocated on top,
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* despite the efforts of the "RAM buffer" approach, which simply rounds
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* memory boundaries up to 64M to try to catch space that may decode
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* as RAM and so is not suitable for MMIO.
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*/
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#define KB(x) ((x) * 1024UL)
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#define MB(x) (KB (KB (x)))
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static resource_size_t __init i830_tseg_size(void)
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{
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u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
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if (!(esmramc & TSEG_ENABLE))
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return 0;
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if (esmramc & I830_TSEG_SIZE_1M)
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return MB(1);
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else
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return KB(512);
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}
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static resource_size_t __init i845_tseg_size(void)
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{
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u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
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u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
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if (!(esmramc & TSEG_ENABLE))
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return 0;
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switch (tseg_size) {
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case I845_TSEG_SIZE_512K: return KB(512);
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case I845_TSEG_SIZE_1M: return MB(1);
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default:
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WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
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}
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return 0;
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}
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static resource_size_t __init i85x_tseg_size(void)
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{
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u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
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if (!(esmramc & TSEG_ENABLE))
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return 0;
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return MB(1);
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}
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static resource_size_t __init i830_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
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}
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static resource_size_t __init i85x_mem_size(void)
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{
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return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
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}
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/*
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* On 830/845/85x the stolen memory base isn't available in any
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* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
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*/
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static resource_size_t __init i830_stolen_base(int num, int slot, int func,
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resource_size_t stolen_size)
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{
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return i830_mem_size() - i830_tseg_size() - stolen_size;
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}
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static resource_size_t __init i845_stolen_base(int num, int slot, int func,
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resource_size_t stolen_size)
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{
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return i830_mem_size() - i845_tseg_size() - stolen_size;
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}
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static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
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resource_size_t stolen_size)
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{
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return i85x_mem_size() - i85x_tseg_size() - stolen_size;
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}
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static resource_size_t __init i865_stolen_base(int num, int slot, int func,
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resource_size_t stolen_size)
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{
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u16 toud = 0;
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toud = read_pci_config_16(0, 0, 0, I865_TOUD);
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return toud * KB(64) + i845_tseg_size();
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}
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static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
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resource_size_t stolen_size)
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{
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u32 bsm;
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/* Almost universally we can find the Graphics Base of Stolen Memory
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* at register BSM (0x5c) in the igfx configuration space. On a few
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* (desktop) machines this is also mirrored in the bridge device at
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* different locations, or in the MCHBAR.
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*/
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bsm = read_pci_config(num, slot, func, INTEL_BSM);
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return bsm & INTEL_BSM_MASK;
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}
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static resource_size_t __init gen11_stolen_base(int num, int slot, int func,
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resource_size_t stolen_size)
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{
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u64 bsm;
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bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0);
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bsm &= INTEL_BSM_MASK;
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bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32;
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return bsm;
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}
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static resource_size_t __init i830_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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gms = gmch_ctrl & I830_GMCH_GMS_MASK;
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switch (gms) {
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case I830_GMCH_GMS_STOLEN_512: return KB(512);
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case I830_GMCH_GMS_STOLEN_1024: return MB(1);
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case I830_GMCH_GMS_STOLEN_8192: return MB(8);
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/* local memory isn't part of the normal address space */
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case I830_GMCH_GMS_LOCAL: return 0;
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default:
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WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
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}
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return 0;
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}
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static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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gms = gmch_ctrl & I855_GMCH_GMS_MASK;
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switch (gms) {
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case I855_GMCH_GMS_STOLEN_1M: return MB(1);
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case I855_GMCH_GMS_STOLEN_4M: return MB(4);
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case I855_GMCH_GMS_STOLEN_8M: return MB(8);
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case I855_GMCH_GMS_STOLEN_16M: return MB(16);
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case I855_GMCH_GMS_STOLEN_32M: return MB(32);
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case I915_GMCH_GMS_STOLEN_48M: return MB(48);
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case I915_GMCH_GMS_STOLEN_64M: return MB(64);
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case G33_GMCH_GMS_STOLEN_128M: return MB(128);
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case G33_GMCH_GMS_STOLEN_256M: return MB(256);
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case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
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case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
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case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
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case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
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default:
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WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
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}
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return 0;
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}
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static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
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return gms * MB(32);
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}
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static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
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return gms * MB(32);
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}
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static resource_size_t __init chv_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
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/*
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* 0x0 to 0x10: 32MB increments starting at 0MB
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* 0x11 to 0x16: 4MB increments starting at 8MB
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* 0x17 to 0x1d: 4MB increments start at 36MB
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*/
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if (gms < 0x11)
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return gms * MB(32);
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else if (gms < 0x17)
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return (gms - 0x11) * MB(4) + MB(8);
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else
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return (gms - 0x17) * MB(4) + MB(36);
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}
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static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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u16 gms;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
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/* 0x0 to 0xef: 32MB increments starting at 0MB */
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/* 0xf0 to 0xfe: 4MB increments starting at 4MB */
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if (gms < 0xf0)
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return gms * MB(32);
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else
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return (gms - 0xf0) * MB(4) + MB(4);
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}
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struct intel_early_ops {
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resource_size_t (*stolen_size)(int num, int slot, int func);
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resource_size_t (*stolen_base)(int num, int slot, int func,
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resource_size_t size);
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};
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static const struct intel_early_ops i830_early_ops __initconst = {
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.stolen_base = i830_stolen_base,
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.stolen_size = i830_stolen_size,
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};
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static const struct intel_early_ops i845_early_ops __initconst = {
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.stolen_base = i845_stolen_base,
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.stolen_size = i830_stolen_size,
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};
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static const struct intel_early_ops i85x_early_ops __initconst = {
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.stolen_base = i85x_stolen_base,
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.stolen_size = gen3_stolen_size,
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};
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static const struct intel_early_ops i865_early_ops __initconst = {
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.stolen_base = i865_stolen_base,
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.stolen_size = gen3_stolen_size,
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};
|
|
|
|
static const struct intel_early_ops gen3_early_ops __initconst = {
|
|
.stolen_base = gen3_stolen_base,
|
|
.stolen_size = gen3_stolen_size,
|
|
};
|
|
|
|
static const struct intel_early_ops gen6_early_ops __initconst = {
|
|
.stolen_base = gen3_stolen_base,
|
|
.stolen_size = gen6_stolen_size,
|
|
};
|
|
|
|
static const struct intel_early_ops gen8_early_ops __initconst = {
|
|
.stolen_base = gen3_stolen_base,
|
|
.stolen_size = gen8_stolen_size,
|
|
};
|
|
|
|
static const struct intel_early_ops gen9_early_ops __initconst = {
|
|
.stolen_base = gen3_stolen_base,
|
|
.stolen_size = gen9_stolen_size,
|
|
};
|
|
|
|
static const struct intel_early_ops chv_early_ops __initconst = {
|
|
.stolen_base = gen3_stolen_base,
|
|
.stolen_size = chv_stolen_size,
|
|
};
|
|
|
|
static const struct intel_early_ops gen11_early_ops __initconst = {
|
|
.stolen_base = gen11_stolen_base,
|
|
.stolen_size = gen9_stolen_size,
|
|
};
|
|
|
|
static const struct pci_device_id intel_early_ids[] __initconst = {
|
|
INTEL_I830_IDS(&i830_early_ops),
|
|
INTEL_I845G_IDS(&i845_early_ops),
|
|
INTEL_I85X_IDS(&i85x_early_ops),
|
|
INTEL_I865G_IDS(&i865_early_ops),
|
|
INTEL_I915G_IDS(&gen3_early_ops),
|
|
INTEL_I915GM_IDS(&gen3_early_ops),
|
|
INTEL_I945G_IDS(&gen3_early_ops),
|
|
INTEL_I945GM_IDS(&gen3_early_ops),
|
|
INTEL_VLV_IDS(&gen6_early_ops),
|
|
INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
|
|
INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
|
|
INTEL_I965G_IDS(&gen3_early_ops),
|
|
INTEL_G33_IDS(&gen3_early_ops),
|
|
INTEL_I965GM_IDS(&gen3_early_ops),
|
|
INTEL_GM45_IDS(&gen3_early_ops),
|
|
INTEL_G45_IDS(&gen3_early_ops),
|
|
INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
|
|
INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
|
|
INTEL_SNB_D_IDS(&gen6_early_ops),
|
|
INTEL_SNB_M_IDS(&gen6_early_ops),
|
|
INTEL_IVB_M_IDS(&gen6_early_ops),
|
|
INTEL_IVB_D_IDS(&gen6_early_ops),
|
|
INTEL_HSW_IDS(&gen6_early_ops),
|
|
INTEL_BDW_IDS(&gen8_early_ops),
|
|
INTEL_CHV_IDS(&chv_early_ops),
|
|
INTEL_SKL_IDS(&gen9_early_ops),
|
|
INTEL_BXT_IDS(&gen9_early_ops),
|
|
INTEL_KBL_IDS(&gen9_early_ops),
|
|
INTEL_CFL_IDS(&gen9_early_ops),
|
|
INTEL_GLK_IDS(&gen9_early_ops),
|
|
INTEL_CNL_IDS(&gen9_early_ops),
|
|
INTEL_ICL_11_IDS(&gen11_early_ops),
|
|
INTEL_EHL_IDS(&gen11_early_ops),
|
|
INTEL_TGL_12_IDS(&gen11_early_ops),
|
|
};
|
|
|
|
struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
|
|
EXPORT_SYMBOL(intel_graphics_stolen_res);
|
|
|
|
static void __init
|
|
intel_graphics_stolen(int num, int slot, int func,
|
|
const struct intel_early_ops *early_ops)
|
|
{
|
|
resource_size_t base, size;
|
|
resource_size_t end;
|
|
|
|
size = early_ops->stolen_size(num, slot, func);
|
|
base = early_ops->stolen_base(num, slot, func, size);
|
|
|
|
if (!size || !base)
|
|
return;
|
|
|
|
end = base + size - 1;
|
|
|
|
intel_graphics_stolen_res.start = base;
|
|
intel_graphics_stolen_res.end = end;
|
|
|
|
printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
|
|
&intel_graphics_stolen_res);
|
|
|
|
/* Mark this space as reserved */
|
|
e820__range_add(base, size, E820_TYPE_RESERVED);
|
|
e820__update_table(e820_table);
|
|
}
|
|
|
|
static void __init intel_graphics_quirks(int num, int slot, int func)
|
|
{
|
|
const struct intel_early_ops *early_ops;
|
|
u16 device;
|
|
int i;
|
|
|
|
device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
|
|
kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
|
|
|
|
if (intel_early_ids[i].device != device)
|
|
continue;
|
|
|
|
early_ops = (typeof(early_ops))driver_data;
|
|
|
|
intel_graphics_stolen(num, slot, func, early_ops);
|
|
|
|
return;
|
|
}
|
|
}
|
|
|
|
static void __init force_disable_hpet(int num, int slot, int func)
|
|
{
|
|
#ifdef CONFIG_HPET_TIMER
|
|
boot_hpet_disable = true;
|
|
pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
|
|
#endif
|
|
}
|
|
|
|
#define BCM4331_MMIO_SIZE 16384
|
|
#define BCM4331_PM_CAP 0x40
|
|
#define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
|
|
#define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
|
|
|
|
static void __init apple_airport_reset(int bus, int slot, int func)
|
|
{
|
|
void __iomem *mmio;
|
|
u16 pmcsr;
|
|
u64 addr;
|
|
int i;
|
|
|
|
if (!x86_apple_machine)
|
|
return;
|
|
|
|
/* Card may have been put into PCI_D3hot by grub quirk */
|
|
pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
|
|
|
|
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
|
|
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
|
|
write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
|
|
mdelay(10);
|
|
|
|
pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
|
|
if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
|
|
pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
|
|
bus, slot, func);
|
|
return;
|
|
}
|
|
}
|
|
|
|
addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
|
|
addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
|
|
addr &= PCI_BASE_ADDRESS_MEM_MASK;
|
|
|
|
mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
|
|
if (!mmio) {
|
|
pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
|
|
bus, slot, func);
|
|
return;
|
|
}
|
|
|
|
pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
|
|
|
|
for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
|
|
udelay(10);
|
|
|
|
bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
|
|
bcma_aread32(BCMA_RESET_CTL);
|
|
udelay(1);
|
|
|
|
bcma_awrite32(BCMA_RESET_CTL, 0);
|
|
bcma_aread32(BCMA_RESET_CTL);
|
|
udelay(10);
|
|
|
|
early_iounmap(mmio, BCM4331_MMIO_SIZE);
|
|
}
|
|
|
|
#define QFLAG_APPLY_ONCE 0x1
|
|
#define QFLAG_APPLIED 0x2
|
|
#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
|
|
struct chipset {
|
|
u32 vendor;
|
|
u32 device;
|
|
u32 class;
|
|
u32 class_mask;
|
|
u32 flags;
|
|
void (*f)(int num, int slot, int func);
|
|
};
|
|
|
|
static struct chipset early_qrk[] __initdata = {
|
|
{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
|
|
{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
|
|
PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
|
|
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
|
|
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
|
|
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
|
|
{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
|
|
PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
|
|
{ PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
|
{ PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
|
{ PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
|
|
PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
|
|
{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
|
|
QFLAG_APPLY_ONCE, intel_graphics_quirks },
|
|
/*
|
|
* HPET on the current version of the Baytrail platform has accuracy
|
|
* problems: it will halt in deep idle state - so we disable it.
|
|
*
|
|
* More details can be found in section 18.10.1.3 of the datasheet:
|
|
*
|
|
* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
|
|
*/
|
|
{ PCI_VENDOR_ID_INTEL, 0x0f00,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
|
|
{ PCI_VENDOR_ID_INTEL, 0x3e20,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
|
|
{ PCI_VENDOR_ID_INTEL, 0x3ec4,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
|
|
{ PCI_VENDOR_ID_INTEL, 0x8a12,
|
|
PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
|
|
{ PCI_VENDOR_ID_BROADCOM, 0x4331,
|
|
PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
|
|
{}
|
|
};
|
|
|
|
static void __init early_pci_scan_bus(int bus);
|
|
|
|
/**
|
|
* check_dev_quirk - apply early quirks to a given PCI device
|
|
* @num: bus number
|
|
* @slot: slot number
|
|
* @func: PCI function
|
|
*
|
|
* Check the vendor & device ID against the early quirks table.
|
|
*
|
|
* If the device is single function, let early_pci_scan_bus() know so we don't
|
|
* poke at this device again.
|
|
*/
|
|
static int __init check_dev_quirk(int num, int slot, int func)
|
|
{
|
|
u16 class;
|
|
u16 vendor;
|
|
u16 device;
|
|
u8 type;
|
|
u8 sec;
|
|
int i;
|
|
|
|
class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
|
|
|
|
if (class == 0xffff)
|
|
return -1; /* no class, treat as single function */
|
|
|
|
vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
|
|
|
|
device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
|
|
|
|
for (i = 0; early_qrk[i].f != NULL; i++) {
|
|
if (((early_qrk[i].vendor == PCI_ANY_ID) ||
|
|
(early_qrk[i].vendor == vendor)) &&
|
|
((early_qrk[i].device == PCI_ANY_ID) ||
|
|
(early_qrk[i].device == device)) &&
|
|
(!((early_qrk[i].class ^ class) &
|
|
early_qrk[i].class_mask))) {
|
|
if ((early_qrk[i].flags &
|
|
QFLAG_DONE) != QFLAG_DONE)
|
|
early_qrk[i].f(num, slot, func);
|
|
early_qrk[i].flags |= QFLAG_APPLIED;
|
|
}
|
|
}
|
|
|
|
type = read_pci_config_byte(num, slot, func,
|
|
PCI_HEADER_TYPE);
|
|
|
|
if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
|
|
sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
|
|
if (sec > num)
|
|
early_pci_scan_bus(sec);
|
|
}
|
|
|
|
if (!(type & 0x80))
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __init early_pci_scan_bus(int bus)
|
|
{
|
|
int slot, func;
|
|
|
|
/* Poor man's PCI discovery */
|
|
for (slot = 0; slot < 32; slot++)
|
|
for (func = 0; func < 8; func++) {
|
|
/* Only probe function 0 on single fn devices */
|
|
if (check_dev_quirk(bus, slot, func))
|
|
break;
|
|
}
|
|
}
|
|
|
|
void __init early_quirks(void)
|
|
{
|
|
if (!early_pci_allowed())
|
|
return;
|
|
|
|
early_pci_scan_bus(0);
|
|
}
|