519 lines
17 KiB
C
519 lines
17 KiB
C
/*
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*
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* Programmable Interrupt Controller functions for the Freescale MPC52xx.
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*
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* Copyright (C) 2008 Secret Lab Technologies Ltd.
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* Copyright (C) 2006 bplan GmbH
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* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 Montavista Software, Inc
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*
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* Based on the code from the 2.4 kernel by
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* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*
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*/
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/*
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* This is the device driver for the MPC5200 interrupt controller.
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*
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* hardware overview
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* -----------------
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* The MPC5200 interrupt controller groups the all interrupt sources into
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* three groups called 'critical', 'main', and 'peripheral'. The critical
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* group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
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* sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
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* gpios, and the general purpose timers. Peripheral group contains the
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* remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
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* USB, DMA, etc).
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*
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* virqs
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* -----
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* The Linux IRQ subsystem requires that each irq source be assigned a
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* system wide unique IRQ number starting at 1 (0 means no irq). Since
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* systems can have multiple interrupt controllers, the virtual IRQ (virq)
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* infrastructure lets each interrupt controller to define a local set
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* of IRQ numbers and the virq infrastructure maps those numbers into
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* a unique range of the global IRQ# space.
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*
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* To define a range of virq numbers for this controller, this driver first
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* assigns a number to each of the irq groups (called the level 1 or L1
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* value). Within each group individual irq sources are also assigned a
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* number, as defined by the MPC5200 user guide, and refers to it as the
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* level 2 or L2 value. The virq number is determined by shifting up the
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* L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
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*
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* For example, the TMR0 interrupt is irq 9 in the main group. The
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* virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
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*
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* The observant reader will also notice that this driver defines a 4th
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* interrupt group called 'bestcomm'. The bestcomm group isn't physically
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* part of the MPC5200 interrupt controller, but it is used here to assign
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* a separate virq number for each bestcomm task (since any of the 16
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* bestcomm tasks can cause the bestcomm interrupt to be raised). When a
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* bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
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* which task needs servicing and returns the irq number for that task. This
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* allows drivers which use bestcomm to define their own interrupt handlers.
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*
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* irq_chip structures
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* -------------------
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* For actually manipulating IRQs (masking, enabling, clearing, etc) this
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* driver defines four separate 'irq_chip' structures, one for the main
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* group, one for the peripherals group, one for the bestcomm group and one
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* for external interrupts. The irq_chip structures provide the hooks needed
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* to manipulate each IRQ source, and since each group is has a separate set
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* of registers for controlling the irq, it makes sense to divide up the
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* hooks along those lines.
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*
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* You'll notice that there is not an irq_chip for the critical group and
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* you'll also notice that there is an irq_chip defined for external
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* interrupts even though there is no external interrupt group. The reason
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* for this is that the four external interrupts are all managed with the same
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* register even though one of the external IRQs is in the critical group and
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* the other three are in the main group. For this reason it makes sense for
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* the 4 external irqs to be managed using a separate set of hooks. The
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* reason there is no crit irq_chip is that of the 3 irqs in the critical
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* group, only external interrupt is actually support at this time by this
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* driver and since external interrupt is the only one used, it can just
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* be directed to make use of the external irq irq_chip.
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*
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* device tree bindings
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* --------------------
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* The device tree bindings for this controller reflect the two level
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* organization of irqs in the device. #interrupt-cells = <3> where the
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* first cell is the group number [0..3], the second cell is the irq
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* number in the group, and the third cell is the sense type (level/edge).
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* For reference, the following is a list of the interrupt property values
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* associated with external interrupt sources on the MPC5200 (just because
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* it is non-obvious to determine what the interrupts property should be
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* when reading the mpc5200 manual and it is a frequently asked question).
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*
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* External interrupts:
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* <0 0 n> external irq0, n is sense (n=0: level high,
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* <1 1 n> external irq1, n is sense n=1: edge rising,
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* <1 2 n> external irq2, n is sense n=2: edge falling,
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* <1 3 n> external irq3, n is sense n=3: level low)
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*/
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#undef DEBUG
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/mpc52xx.h>
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/* HW IRQ mapping */
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#define MPC52xx_IRQ_L1_CRIT (0)
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#define MPC52xx_IRQ_L1_MAIN (1)
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#define MPC52xx_IRQ_L1_PERP (2)
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#define MPC52xx_IRQ_L1_SDMA (3)
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#define MPC52xx_IRQ_L1_OFFSET (6)
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#define MPC52xx_IRQ_L1_MASK (0x00c0)
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#define MPC52xx_IRQ_L2_MASK (0x003f)
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#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
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/* MPC5200 device tree match tables */
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static const struct of_device_id mpc52xx_pic_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-pic", },
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{ .compatible = "mpc5200-pic", },
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{}
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};
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static const struct of_device_id mpc52xx_sdma_ids[] __initconst = {
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{ .compatible = "fsl,mpc5200-bestcomm", },
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{ .compatible = "mpc5200-bestcomm", },
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{}
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};
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static struct mpc52xx_intr __iomem *intr;
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static struct mpc52xx_sdma __iomem *sdma;
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static struct irq_domain *mpc52xx_irqhost = NULL;
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static unsigned char mpc52xx_map_senses[4] = {
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_RISING,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_LEVEL_LOW,
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};
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/* Utility functions */
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static inline void io_be_setbit(u32 __iomem *addr, int bitno)
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{
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out_be32(addr, in_be32(addr) | (1 << bitno));
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}
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static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
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{
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out_be32(addr, in_be32(addr) & ~(1 << bitno));
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}
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/*
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* IRQ[0-3] interrupt irq_chip
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*/
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static void mpc52xx_extirq_mask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_clrbit(&intr->ctrl, 11 - l2irq);
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}
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static void mpc52xx_extirq_unmask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_setbit(&intr->ctrl, 11 - l2irq);
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}
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static void mpc52xx_extirq_ack(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_setbit(&intr->ctrl, 27-l2irq);
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}
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static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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u32 ctrl_reg, type;
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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void *handler = handle_level_irq;
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pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__,
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(int) irqd_to_hwirq(d), l2irq, flow_type);
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switch (flow_type) {
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case IRQF_TRIGGER_HIGH: type = 0; break;
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case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
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case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
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case IRQF_TRIGGER_LOW: type = 3; break;
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default:
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type = 0;
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}
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ctrl_reg = in_be32(&intr->ctrl);
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ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
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ctrl_reg |= (type << (22 - (l2irq * 2)));
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out_be32(&intr->ctrl, ctrl_reg);
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irq_set_handler_locked(d, handler);
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return 0;
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}
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static struct irq_chip mpc52xx_extirq_irqchip = {
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.name = "MPC52xx External",
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.irq_mask = mpc52xx_extirq_mask,
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.irq_unmask = mpc52xx_extirq_unmask,
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.irq_ack = mpc52xx_extirq_ack,
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.irq_set_type = mpc52xx_extirq_set_type,
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};
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/*
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* Main interrupt irq_chip
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*/
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static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type)
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{
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return 0; /* Do nothing so that the sense mask will get updated */
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}
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static void mpc52xx_main_mask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_setbit(&intr->main_mask, 16 - l2irq);
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}
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static void mpc52xx_main_unmask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_clrbit(&intr->main_mask, 16 - l2irq);
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}
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static struct irq_chip mpc52xx_main_irqchip = {
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.name = "MPC52xx Main",
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.irq_mask = mpc52xx_main_mask,
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.irq_mask_ack = mpc52xx_main_mask,
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.irq_unmask = mpc52xx_main_unmask,
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.irq_set_type = mpc52xx_null_set_type,
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};
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/*
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* Peripherals interrupt irq_chip
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*/
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static void mpc52xx_periph_mask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_setbit(&intr->per_mask, 31 - l2irq);
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}
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static void mpc52xx_periph_unmask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_clrbit(&intr->per_mask, 31 - l2irq);
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}
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static struct irq_chip mpc52xx_periph_irqchip = {
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.name = "MPC52xx Peripherals",
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.irq_mask = mpc52xx_periph_mask,
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.irq_mask_ack = mpc52xx_periph_mask,
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.irq_unmask = mpc52xx_periph_unmask,
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.irq_set_type = mpc52xx_null_set_type,
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};
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/*
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* SDMA interrupt irq_chip
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*/
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static void mpc52xx_sdma_mask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_setbit(&sdma->IntMask, l2irq);
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}
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static void mpc52xx_sdma_unmask(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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io_be_clrbit(&sdma->IntMask, l2irq);
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}
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static void mpc52xx_sdma_ack(struct irq_data *d)
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{
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int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
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out_be32(&sdma->IntPend, 1 << l2irq);
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}
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static struct irq_chip mpc52xx_sdma_irqchip = {
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.name = "MPC52xx SDMA",
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.irq_mask = mpc52xx_sdma_mask,
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.irq_unmask = mpc52xx_sdma_unmask,
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.irq_ack = mpc52xx_sdma_ack,
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.irq_set_type = mpc52xx_null_set_type,
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};
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/**
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* mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
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*/
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static int mpc52xx_is_extirq(int l1, int l2)
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{
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return ((l1 == 0) && (l2 == 0)) ||
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((l1 == 1) && (l2 >= 1) && (l2 <= 3));
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}
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/**
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* mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
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*/
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static int mpc52xx_irqhost_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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int intrvect_l1;
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int intrvect_l2;
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int intrvect_type;
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int intrvect_linux;
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if (intsize != 3)
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return -1;
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intrvect_l1 = (int)intspec[0];
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intrvect_l2 = (int)intspec[1];
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intrvect_type = (int)intspec[2] & 0x3;
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intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
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MPC52xx_IRQ_L1_MASK;
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intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
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*out_hwirq = intrvect_linux;
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*out_flags = IRQ_TYPE_LEVEL_LOW;
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if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
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*out_flags = mpc52xx_map_senses[intrvect_type];
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pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
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intrvect_l2);
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return 0;
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}
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/**
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* mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
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*/
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static int mpc52xx_irqhost_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t irq)
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{
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int l1irq;
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int l2irq;
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struct irq_chip *uninitialized_var(irqchip);
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void *hndlr;
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int type;
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u32 reg;
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l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
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l2irq = irq & MPC52xx_IRQ_L2_MASK;
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/*
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* External IRQs are handled differently by the hardware so they are
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* handled by a dedicated irq_chip structure.
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*/
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if (mpc52xx_is_extirq(l1irq, l2irq)) {
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reg = in_be32(&intr->ctrl);
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type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
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if ((type == IRQ_TYPE_EDGE_FALLING) ||
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(type == IRQ_TYPE_EDGE_RISING))
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hndlr = handle_edge_irq;
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else
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hndlr = handle_level_irq;
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irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
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pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
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__func__, l2irq, virq, (int)irq, type);
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return 0;
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}
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/* It is an internal SOC irq. Choose the correct irq_chip */
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switch (l1irq) {
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case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
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case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
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case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
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case MPC52xx_IRQ_L1_CRIT:
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pr_warn("%s: Critical IRQ #%d is unsupported! Nopping it.\n",
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__func__, l2irq);
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irq_set_chip(virq, &no_irq_chip);
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return 0;
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}
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irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
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pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
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return 0;
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}
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static const struct irq_domain_ops mpc52xx_irqhost_ops = {
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.xlate = mpc52xx_irqhost_xlate,
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.map = mpc52xx_irqhost_map,
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};
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/**
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* mpc52xx_init_irq - Initialize and register with the virq subsystem
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*
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* Hook for setting up IRQs on an mpc5200 system. A pointer to this function
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* is to be put into the machine definition structure.
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*
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* This function searches the device tree for an MPC5200 interrupt controller,
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* initializes it, and registers it with the virq subsystem.
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*/
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void __init mpc52xx_init_irq(void)
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{
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u32 intr_ctrl;
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struct device_node *picnode;
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struct device_node *np;
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/* Remap the necessary zones */
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picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
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intr = of_iomap(picnode, 0);
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if (!intr)
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panic(__FILE__ ": find_and_map failed on 'mpc5200-pic'. "
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"Check node !");
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np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
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sdma = of_iomap(np, 0);
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of_node_put(np);
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if (!sdma)
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panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
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"Check node !");
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pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
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/* Disable all interrupt sources. */
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out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
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out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
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out_be32(&intr->per_mask, 0x7ffffc00); /* 1 means disabled */
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out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
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intr_ctrl = in_be32(&intr->ctrl);
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intr_ctrl &= 0x00ff0000; /* Keeps IRQ[0-3] config */
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intr_ctrl |= 0x0f000000 | /* clear IRQ 0-3 */
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0x00001000 | /* MEE master external enable */
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0x00000000 | /* 0 means disable IRQ 0-3 */
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0x00000001; /* CEb route critical normally */
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out_be32(&intr->ctrl, intr_ctrl);
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/* Zero a bunch of the priority settings. */
|
|
out_be32(&intr->per_pri1, 0);
|
|
out_be32(&intr->per_pri2, 0);
|
|
out_be32(&intr->per_pri3, 0);
|
|
out_be32(&intr->main_pri1, 0);
|
|
out_be32(&intr->main_pri2, 0);
|
|
|
|
/*
|
|
* As last step, add an irq host to translate the real
|
|
* hw irq information provided by the ofw to linux virq
|
|
*/
|
|
mpc52xx_irqhost = irq_domain_add_linear(picnode,
|
|
MPC52xx_IRQ_HIGHTESTHWIRQ,
|
|
&mpc52xx_irqhost_ops, NULL);
|
|
|
|
if (!mpc52xx_irqhost)
|
|
panic(__FILE__ ": Cannot allocate the IRQ host\n");
|
|
|
|
irq_set_default_host(mpc52xx_irqhost);
|
|
|
|
pr_info("MPC52xx PIC is up and running!\n");
|
|
}
|
|
|
|
/**
|
|
* mpc52xx_get_irq - Get pending interrupt number hook function
|
|
*
|
|
* Called by the interrupt handler to determine what IRQ handler needs to be
|
|
* executed.
|
|
*
|
|
* Status of pending interrupts is determined by reading the encoded status
|
|
* register. The encoded status register has three fields; one for each of the
|
|
* types of interrupts defined by the controller - 'critical', 'main' and
|
|
* 'peripheral'. This function reads the status register and returns the IRQ
|
|
* number associated with the highest priority pending interrupt. 'Critical'
|
|
* interrupts have the highest priority, followed by 'main' interrupts, and
|
|
* then 'peripheral'.
|
|
*
|
|
* The mpc5200 interrupt controller can be configured to boost the priority
|
|
* of individual 'peripheral' interrupts. If this is the case then a special
|
|
* value will appear in either the crit or main fields indicating a high
|
|
* or medium priority peripheral irq has occurred.
|
|
*
|
|
* This function checks each of the 3 irq request fields and returns the
|
|
* first pending interrupt that it finds.
|
|
*
|
|
* This function also identifies a 4th type of interrupt; 'bestcomm'. Each
|
|
* bestcomm DMA task can raise the bestcomm peripheral interrupt. When this
|
|
* occurs at task-specific IRQ# is decoded so that each task can have its
|
|
* own IRQ handler.
|
|
*/
|
|
unsigned int mpc52xx_get_irq(void)
|
|
{
|
|
u32 status;
|
|
int irq;
|
|
|
|
status = in_be32(&intr->enc_status);
|
|
if (status & 0x00000400) { /* critical */
|
|
irq = (status >> 8) & 0x3;
|
|
if (irq == 2) /* high priority peripheral */
|
|
goto peripheral;
|
|
irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
|
|
} else if (status & 0x00200000) { /* main */
|
|
irq = (status >> 16) & 0x1f;
|
|
if (irq == 4) /* low priority peripheral */
|
|
goto peripheral;
|
|
irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
|
|
} else if (status & 0x20000000) { /* peripheral */
|
|
peripheral:
|
|
irq = (status >> 24) & 0x1f;
|
|
if (irq == 0) { /* bestcomm */
|
|
status = in_be32(&sdma->IntPend);
|
|
irq = ffs(status) - 1;
|
|
irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
|
|
} else {
|
|
irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
|
|
}
|
|
} else {
|
|
return 0;
|
|
}
|
|
|
|
return irq_linear_revmap(mpc52xx_irqhost, irq);
|
|
}
|