120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
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#define _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
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#ifdef __KERNEL__
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/* PTE bit definitions for processors compliant to the Book3E
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* architecture 2.06 or later. The position of the PTE bits
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* matches the HW definition of the optional Embedded Page Table
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* category.
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*/
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/* Architected bits */
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#define _PAGE_PRESENT 0x000001 /* software: pte contains a translation */
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#define _PAGE_SW1 0x000002
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#define _PAGE_BIT_SWAP_TYPE 2
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#define _PAGE_BAP_SR 0x000004
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#define _PAGE_BAP_UR 0x000008
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#define _PAGE_BAP_SW 0x000010
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#define _PAGE_BAP_UW 0x000020
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#define _PAGE_BAP_SX 0x000040
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#define _PAGE_BAP_UX 0x000080
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#define _PAGE_PSIZE_MSK 0x000f00
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#define _PAGE_PSIZE_4K 0x000200
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#define _PAGE_PSIZE_8K 0x000300
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#define _PAGE_PSIZE_16K 0x000400
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#define _PAGE_PSIZE_32K 0x000500
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#define _PAGE_PSIZE_64K 0x000600
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#define _PAGE_PSIZE_128K 0x000700
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#define _PAGE_PSIZE_256K 0x000800
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#define _PAGE_PSIZE_512K 0x000900
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#define _PAGE_PSIZE_1M 0x000a00
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#define _PAGE_PSIZE_2M 0x000b00
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#define _PAGE_PSIZE_4M 0x000c00
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#define _PAGE_PSIZE_8M 0x000d00
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#define _PAGE_PSIZE_16M 0x000e00
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#define _PAGE_PSIZE_32M 0x000f00
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#define _PAGE_DIRTY 0x001000 /* C: page changed */
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#define _PAGE_SW0 0x002000
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#define _PAGE_U3 0x004000
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#define _PAGE_U2 0x008000
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#define _PAGE_U1 0x010000
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#define _PAGE_U0 0x020000
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#define _PAGE_ACCESSED 0x040000
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#define _PAGE_ENDIAN 0x080000
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#define _PAGE_GUARDED 0x100000
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#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
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#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
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/* "Higher level" linux bit combinations */
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#define _PAGE_EXEC _PAGE_BAP_UX /* .. and was cache cleaned */
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#define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
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#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
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#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_PRIVILEGED (_PAGE_BAP_SR)
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#define _PAGE_SPECIAL _PAGE_SW0
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/* Base page size */
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#define _PAGE_PSIZE _PAGE_PSIZE_4K
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#define PTE_RPN_SHIFT (24)
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#define PTE_WIMGE_SHIFT (19)
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#define PTE_BAP_SHIFT (2)
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/* On 32-bit, we never clear the top part of the PTE */
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#ifdef CONFIG_PPC32
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#define _PTE_NONE_MASK 0xffffffff00000000ULL
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#define _PMD_USER 0
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#else
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#define _PTE_NONE_MASK 0
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#endif
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/*
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* We define 2 sets of base prot bits, one for basic pages (ie,
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* cacheable kernel and user pages) and one for non cacheable
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* pages. We always set _PAGE_COHERENT when SMP is enabled or
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* the processor might need it for DMA coherency.
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*/
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
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#if defined(CONFIG_SMP)
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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#else
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#define _PAGE_BASE (_PAGE_BASE_NC)
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#endif
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/* Permission masks used to generate the __P and __S table */
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#define PAGE_NONE __pgprot(_PAGE_BASE)
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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#ifndef __ASSEMBLY__
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static inline pte_t pte_mkprivileged(pte_t pte)
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{
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return __pte((pte_val(pte) & ~_PAGE_USER) | _PAGE_PRIVILEGED);
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}
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#define pte_mkprivileged pte_mkprivileged
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static inline pte_t pte_mkuser(pte_t pte)
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{
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return __pte((pte_val(pte) & ~_PAGE_PRIVILEGED) | _PAGE_USER);
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}
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#define pte_mkuser pte_mkuser
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */
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