118 lines
3.3 KiB
Plaintext
118 lines
3.3 KiB
Plaintext
/*
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* B4860DS Device Tree Source
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*
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* Copyright 2012 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "b4860si-pre.dtsi"
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/include/ "b4qds.dtsi"
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/ {
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model = "fsl,B4860QDS";
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compatible = "fsl,B4860QDS";
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aliases {
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phy_sgmii_1e = &phy_sgmii_1e;
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phy_sgmii_1f = &phy_sgmii_1f;
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phy_xaui_slot1 = &phy_xaui_slot1;
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phy_xaui_slot2 = &phy_xaui_slot2;
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};
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ifc: localbus@ffe124000 {
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board-control@3,0 {
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compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
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};
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};
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soc@ffe000000 {
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fman@400000 {
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ethernet@e8000 {
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phy-handle = <&phy_sgmii_1e>;
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phy-connection-type = "sgmii";
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};
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ethernet@ea000 {
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phy-handle = <&phy_sgmii_1f>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 {
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phy-handle = <&phy_xaui_slot1>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&phy_xaui_slot2>;
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phy-connection-type = "xgmii";
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};
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mdio@fc000 {
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phy_sgmii_1e: ethernet-phy@1e {
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reg = <0x1e>;
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status = "disabled";
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};
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phy_sgmii_1f: ethernet-phy@1f {
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reg = <0x1f>;
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status = "disabled";
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};
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};
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mdio@fd000 {
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phy_xaui_slot1: xaui-phy@slot1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x7>;
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status = "disabled";
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};
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phy_xaui_slot2: xaui-phy@slot2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x6>;
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status = "disabled";
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};
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};
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};
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};
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rio: rapidio@ffe0c0000 {
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reg = <0xf 0xfe0c0000 0 0x11000>;
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port1 {
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ranges = <0 0 0xc 0x20000000 0 0x10000000>;
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};
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port2 {
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ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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};
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};
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};
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/include/ "b4860si-post.dtsi"
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