STMicroelectronics STM32 USB HS PHY controller The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI switch. It controls PHY configuration and status, and the UTMI+ switch that selects either OTG or HOST controller for the second PHY port. It also sets PLL configuration. USBPHYC |_ PLL | |_ PHY port#1 _________________ HOST controller | _ | | / 1|________________| |_ PHY port#2 ----| |________________ | \_0| | |_ UTMI switch_______| OTG controller Phy provider node ================= Required properties: - compatible: must be "st,stm32mp1-usbphyc" - reg: address and length of the usb phy control register set - clocks: phandle + clock specifier for the PLL phy clock - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY - #address-cells: number of address cells for phys sub-nodes, must be <1> - #size-cells: number of size cells for phys sub-nodes, must be <0> - #clock-cells: number of clock cells for ck_usbo_48m consumer, must be <0> Optional properties: - assigned-clocks: phandle + clock specifier for the PLL phy clock - assigned-clock-parents: the PLL phy clock parent - resets: phandle + reset specifier Required nodes: one sub-node per port the controller provides. Phy sub-nodes ============= Required properties: - reg: phy port index - phy-supply: phandle to the regulator providing 3V3 power to the PHY, see phy-bindings.txt in the same directory. - #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY port#1 and must be <1> for PHY port#2, to select USB controller Optional properties: - st,phy-tuning : phandle to the usb phy tuning node, see Phy tuning node below Phy tuning node =============== It may be necessary to adjust the phy settings to compensate parasitics, which can be due to USB connector/receptacle, routing, ESD protection component, ... Here is the list of all optional parameters to tune the interface of the phy (HS for High-Speed, FS for Full-Speed, LS for Low-Speed) Optional properties: - st,current-boost: <1> current boosting of 1mA <2> current boosting of 2mA - st,no-lsfs-fb-cap: disables the LS/FS feedback capacitor - st,hs-slew-ctrl: slows the HS driver slew rate by 10% - st,hs-dc-level: <0> decreases the HS driver DC level by 5 to 7mV <1> increases the HS driver DC level by 5 to 7mV <2> increases the HS driver DC level by 10 to 14mV - st,fs-rftime-tuning: enables the FS rise/fall tuning option - st,hs-rftime-reduction: enables the HS rise/fall reduction feature - st,hs-current-trim: controls HS driver current trimming for choke - st,hs-impedance-trim: controls HS driver impedance tuning for choke - st,squelch-level: adjusts the squelch DC threshold value - st,hs-rx-gain-eq: enables the HS Rx gain equalizer - st,hs-rx-offset: adjusts the HS Rx offset - st,no-hs-ftime-ctrl: disables the HS fall time control of single ended signals during pre-emphasis - st,no-lsfs-sc: disables the short circuit protection in LS/FS driver - st,hs-tx-staggering: enables the basic staggering in HS Tx mode Example: usb_phy_tuning: usb-phy-tuning { st,current-boost = <2>; st,no-lfs-fb-cap; st,hs-dc-level = <2>; st,hs-rftime-reduction; st,hs-current-trim = <5>; st,hs-impedance-trim = <0>; st,squelch-level = <1>; st,no-hs-ftime-ctrl; st,hs-tx-staggering; }; usbphyc: usb-phy@5a006000 { compatible = "st,stm32mp1-usbphyc"; reg = <0x5a006000 0x1000>; clocks = <&rcc_clk USBPHY_K>; resets = <&rcc_rst USBPHY_R>; vdda1v1-supply = <®11>; vdda1v8-supply = <®18>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; }; usbphyc_port1: usb-phy@1 { reg = <1>; phy-supply = <&vdd_usb>; #phy-cells = <1>; st,phy-tuning = <&usb_phy_tuning>; }; };