linux/linux-5.4.31/tools/perf/pmu-events/arch/x86/haswellx/frontend.json

[
    {
        "EventCode": "0x79",
        "UMask": "0x2",
        "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.EMPTY",
        "Errata": "HSD135",
        "PublicDescription": "Counts cycles the IDQ is empty.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x4",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MITE_UOPS",
        "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x4",
        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MITE_CYCLES",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x8",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.DSB_UOPS",
        "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x8",
        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.DSB_CYCLES",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x10",
        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_DSB_UOPS",
        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x10",
        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_DSB_CYCLES",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EdgeDetect": "1",
        "EventCode": "0x79",
        "UMask": "0x10",
        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_DSB_OCCUR",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x18",
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
        "CounterMask": "4",
        "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x18",
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
        "CounterMask": "1",
        "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x20",
        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_MITE_UOPS",
        "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x24",
        "BriefDescription": "Cycles MITE is delivering 4 Uops",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
        "CounterMask": "4",
        "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x24",
        "BriefDescription": "Cycles MITE is delivering any Uop",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
        "CounterMask": "1",
        "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x30",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_UOPS",
        "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x30",
        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_CYCLES",
        "CounterMask": "1",
        "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops.  Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder.  Using other instructions, if possible, will usually improve performance.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EdgeDetect": "1",
        "EventCode": "0x79",
        "UMask": "0x30",
        "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MS_SWITCHES",
        "CounterMask": "1",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x79",
        "UMask": "0x3c",
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
        "Counter": "0,1,2,3",
        "EventName": "IDQ.MITE_ALL_UOPS",
        "PublicDescription": "Number of uops delivered to IDQ from any path.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x80",
        "UMask": "0x1",
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
        "Counter": "0,1,2,3",
        "EventName": "ICACHE.HIT",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x80",
        "UMask": "0x2",
        "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
        "Counter": "0,1,2,3",
        "EventName": "ICACHE.MISSES",
        "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.",
        "SampleAfterValue": "200003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x80",
        "UMask": "0x4",
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
        "Counter": "0,1,2,3",
        "EventName": "ICACHE.IFETCH_STALL",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x80",
        "UMask": "0x4",
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
        "Counter": "0,1,2,3",
        "EventName": "ICACHE.IFDATA_STALL",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x9C",
        "UMask": "0x1",
        "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
        "Counter": "0,1,2,3",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
        "Errata": "HSD135",
        "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "UMask": "0x1",
        "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
        "Counter": "0,1,2,3",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
        "CounterMask": "4",
        "Errata": "HSD135",
        "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled.  This event is counted on a per-core basis.",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "UMask": "0x1",
        "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
        "CounterMask": "3",
        "Errata": "HSD135",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "UMask": "0x1",
        "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
        "CounterMask": "2",
        "Errata": "HSD135",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0x9C",
        "UMask": "0x1",
        "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
        "CounterMask": "1",
        "Errata": "HSD135",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "Invert": "1",
        "EventCode": "0x9C",
        "UMask": "0x1",
        "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
        "Counter": "0,1,2,3",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
        "CounterMask": "1",
        "Errata": "HSD135",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "EventCode": "0xAB",
        "UMask": "0x2",
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
        "Counter": "0,1,2,3",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "SampleAfterValue": "2000003",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    }
]