679 lines
28 KiB
JSON
679 lines
28 KiB
JSON
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[
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{
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"EventCode": "0x05",
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"UMask": "0x1",
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"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
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"Counter": "0,1,2,3",
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"EventName": "MISALIGN_MEM_REF.LOADS",
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"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x05",
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"UMask": "0x2",
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"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
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"Counter": "0,1,2,3",
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"EventName": "MISALIGN_MEM_REF.STORES",
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"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x1",
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"BriefDescription": "Number of times a TSX line had a cache conflict",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.ABORT_CONFLICT",
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"PublicDescription": "Number of times a TSX line had a cache conflict.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x2",
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"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
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"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x4",
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"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
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"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x8",
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"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
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"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x10",
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"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
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"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x20",
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"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
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"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x54",
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"UMask": "0x40",
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"BriefDescription": "Number of times we could not allocate Lock Buffer",
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"Counter": "0,1,2,3",
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"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
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"PublicDescription": "Number of times we could not allocate Lock Buffer.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x5d",
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"UMask": "0x1",
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"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
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"Counter": "0,1,2,3",
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"EventName": "TX_EXEC.MISC1",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x5d",
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"UMask": "0x2",
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"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
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"Counter": "0,1,2,3",
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"EventName": "TX_EXEC.MISC2",
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"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x5d",
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"UMask": "0x4",
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"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
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"Counter": "0,1,2,3",
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"EventName": "TX_EXEC.MISC3",
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"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x5d",
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"UMask": "0x8",
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"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
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"Counter": "0,1,2,3",
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"EventName": "TX_EXEC.MISC4",
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"PublicDescription": "RTM region detected inside HLE.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x5d",
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"UMask": "0x10",
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"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
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"Counter": "0,1,2,3",
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"EventName": "TX_EXEC.MISC5",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC3",
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"UMask": "0x2",
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"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
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"Counter": "0,1,2,3",
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"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
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"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
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"SampleAfterValue": "100003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x1",
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"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.START",
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"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x2",
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"BriefDescription": "Number of times HLE commit succeeded",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.COMMIT",
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"PublicDescription": "Number of times HLE commit succeeded.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x4",
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"BriefDescription": "Number of times HLE abort was triggered",
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"PEBS": "1",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.ABORTED",
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"PublicDescription": "Number of times HLE abort was triggered.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x8",
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"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.ABORTED_MISC1",
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"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x10",
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"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.ABORTED_MISC2",
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"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x20",
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"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.ABORTED_MISC3",
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"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x40",
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"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.ABORTED_MISC4",
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"PublicDescription": "Number of times HLE caused a fault.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc8",
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"UMask": "0x80",
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"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
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"Counter": "0,1,2,3",
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"EventName": "HLE_RETIRED.ABORTED_MISC5",
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"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x1",
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"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.START",
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"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x2",
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"BriefDescription": "Number of times RTM commit succeeded",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.COMMIT",
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"PublicDescription": "Number of times RTM commit succeeded.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x4",
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"BriefDescription": "Number of times RTM abort was triggered",
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"PEBS": "1",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.ABORTED",
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"PublicDescription": "Number of times RTM abort was triggered .",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x8",
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"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.ABORTED_MISC1",
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"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x10",
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"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.ABORTED_MISC2",
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"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x20",
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"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.ABORTED_MISC3",
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"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x40",
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"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.ABORTED_MISC4",
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"PublicDescription": "Number of times a RTM caused a fault.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xc9",
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"UMask": "0x80",
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"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
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"Counter": "0,1,2,3",
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"EventName": "RTM_RETIRED.ABORTED_MISC5",
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"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
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|
|
"SampleAfterValue": "2000003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 4",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x4",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above four.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 8",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x8",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above eight.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "50021",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 16",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x10",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above 16.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "20011",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 32",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x20",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above 32.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "100007",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 64",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x40",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above 64.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "2003",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 128",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x80",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above 128.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "1009",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 256",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x100",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above 256.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "503",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"EventCode": "0xCD",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Randomly selected loads with latency value being above 512",
|
||
|
|
"PEBS": "2",
|
||
|
|
"MSRValue": "0x200",
|
||
|
|
"Counter": "3",
|
||
|
|
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
|
||
|
|
"MSRIndex": "0x3F6",
|
||
|
|
"Errata": "BDM100, BDM35",
|
||
|
|
"PublicDescription": "Counts randomly selected loads with latency value being above 512.",
|
||
|
|
"TakenAlone": "1",
|
||
|
|
"SampleAfterValue": "101",
|
||
|
|
"CounterHTOff": "3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all requests miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC08FFF",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all requests miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
|
||
|
|
"MSRValue": "0x087FC007F7",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
|
||
|
|
"MSRValue": "0x103FC007F7",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
|
||
|
|
"MSRValue": "0x063BC007F7",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
|
||
|
|
"MSRValue": "0x06040007F7",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC007F7",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
|
||
|
|
"MSRValue": "0x0604000244",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC00244",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
|
||
|
|
"MSRValue": "0x0604000122",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC00122",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
|
||
|
|
"MSRValue": "0x087FC00091",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
|
||
|
|
"MSRValue": "0x103FC00091",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
|
||
|
|
"MSRValue": "0x063BC00091",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
|
||
|
|
"MSRValue": "0x0604000091",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC00091",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC00200",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC00100",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
|
||
|
|
"MSRValue": "0x103FC00002",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"Offcore": "1",
|
||
|
|
"EventCode": "0xB7, 0xBB",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
|
||
|
|
"MSRValue": "0x3FBFC00002",
|
||
|
|
"Counter": "0,1,2,3",
|
||
|
|
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
|
||
|
|
"MSRIndex": "0x1a6,0x1a7",
|
||
|
|
"PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"CounterHTOff": "0,1,2,3"
|
||
|
|
}
|
||
|
|
]
|