498 lines
14 KiB
C
498 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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// Copyright 2017 IBM Corp.
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#ifndef _MISC_OCXL_H_
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#define _MISC_OCXL_H_
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#include <linux/pci.h>
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/*
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* Opencapi drivers all need some common facilities, like parsing the
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* device configuration space, adding a Process Element to the Shared
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* Process Area, etc...
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*
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* The ocxl module provides a kernel API, to allow other drivers to
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* reuse common code. A bit like a in-kernel library.
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*/
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#define OCXL_AFU_NAME_SZ (24+1) /* add 1 for NULL termination */
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struct ocxl_afu_config {
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u8 idx;
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int dvsec_afu_control_pos; /* offset of AFU control DVSEC */
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char name[OCXL_AFU_NAME_SZ];
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u8 version_major;
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u8 version_minor;
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u8 afuc_type;
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u8 afum_type;
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u8 profile;
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u8 global_mmio_bar; /* global MMIO area */
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u64 global_mmio_offset;
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u32 global_mmio_size;
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u8 pp_mmio_bar; /* per-process MMIO area */
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u64 pp_mmio_offset;
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u32 pp_mmio_stride;
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u64 lpc_mem_offset;
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u64 lpc_mem_size;
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u64 special_purpose_mem_offset;
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u64 special_purpose_mem_size;
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u8 pasid_supported_log;
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u16 actag_supported;
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};
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struct ocxl_fn_config {
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int dvsec_tl_pos; /* offset of the Transaction Layer DVSEC */
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int dvsec_function_pos; /* offset of the Function DVSEC */
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int dvsec_afu_info_pos; /* offset of the AFU information DVSEC */
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s8 max_pasid_log;
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s8 max_afu_index;
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};
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enum ocxl_endian {
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OCXL_BIG_ENDIAN = 0, /**< AFU data is big-endian */
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OCXL_LITTLE_ENDIAN = 1, /**< AFU data is little-endian */
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OCXL_HOST_ENDIAN = 2, /**< AFU data is the same endianness as the host */
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};
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// These are opaque outside the ocxl driver
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struct ocxl_afu;
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struct ocxl_fn;
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struct ocxl_context;
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// Device detection & initialisation
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/**
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* Open an OpenCAPI function on an OpenCAPI device
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*
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* @dev: The PCI device that contains the function
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*
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* Returns an opaque pointer to the function, or an error pointer (check with IS_ERR)
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*/
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struct ocxl_fn *ocxl_function_open(struct pci_dev *dev);
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/**
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* Get the list of AFUs associated with a PCI function device
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*
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* Returns a list of struct ocxl_afu *
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*
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* @fn: The OpenCAPI function containing the AFUs
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*/
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struct list_head *ocxl_function_afu_list(struct ocxl_fn *fn);
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/**
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* Fetch an AFU instance from an OpenCAPI function
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*
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* @fn: The OpenCAPI function to get the AFU from
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* @afu_idx: The index of the AFU to get
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*
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* If successful, the AFU should be released with ocxl_afu_put()
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*
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* Returns a pointer to the AFU, or NULL on error
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*/
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struct ocxl_afu *ocxl_function_fetch_afu(struct ocxl_fn *fn, u8 afu_idx);
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/**
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* Take a reference to an AFU
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*
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* @afu: The AFU to increment the reference count on
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*/
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void ocxl_afu_get(struct ocxl_afu *afu);
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/**
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* Release a reference to an AFU
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*
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* @afu: The AFU to decrement the reference count on
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*/
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void ocxl_afu_put(struct ocxl_afu *afu);
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/**
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* Get the configuration information for an OpenCAPI function
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*
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* @fn: The OpenCAPI function to get the config for
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*
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* Returns the function config, or NULL on error
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*/
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const struct ocxl_fn_config *ocxl_function_config(struct ocxl_fn *fn);
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/**
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* Close an OpenCAPI function
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*
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* This will free any AFUs previously retrieved from the function, and
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* detach and associated contexts. The contexts must by freed by the caller.
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*
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* @fn: The OpenCAPI function to close
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*
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*/
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void ocxl_function_close(struct ocxl_fn *fn);
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// Context allocation
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/**
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* Allocate an OpenCAPI context
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*
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* @context: The OpenCAPI context to allocate, must be freed with ocxl_context_free
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* @afu: The AFU the context belongs to
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* @mapping: The mapping to unmap when the context is closed (may be NULL)
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*/
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int ocxl_context_alloc(struct ocxl_context **context, struct ocxl_afu *afu,
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struct address_space *mapping);
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/**
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* Free an OpenCAPI context
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*
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* @ctx: The OpenCAPI context to free
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*/
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void ocxl_context_free(struct ocxl_context *ctx);
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/**
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* Grant access to an MM to an OpenCAPI context
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* @ctx: The OpenCAPI context to attach
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* @amr: The value of the AMR register to restrict access
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* @mm: The mm to attach to the context
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*
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* Returns 0 on success, negative on failure
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*/
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int ocxl_context_attach(struct ocxl_context *ctx, u64 amr,
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struct mm_struct *mm);
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/**
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* Detach an MM from an OpenCAPI context
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* @ctx: The OpenCAPI context to attach
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*
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* Returns 0 on success, negative on failure
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*/
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int ocxl_context_detach(struct ocxl_context *ctx);
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// AFU IRQs
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/**
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* Allocate an IRQ associated with an AFU context
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* @ctx: the AFU context
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* @irq_id: out, the IRQ ID
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*
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* Returns 0 on success, negative on failure
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*/
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extern int ocxl_afu_irq_alloc(struct ocxl_context *ctx, int *irq_id);
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/**
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* Frees an IRQ associated with an AFU context
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* @ctx: the AFU context
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* @irq_id: the IRQ ID
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*
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* Returns 0 on success, negative on failure
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*/
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extern int ocxl_afu_irq_free(struct ocxl_context *ctx, int irq_id);
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/**
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* Gets the address of the trigger page for an IRQ
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* This can then be provided to an AFU which will write to that
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* page to trigger the IRQ.
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* @ctx: The AFU context that the IRQ is associated with
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* @irq_id: The IRQ ID
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*
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* returns the trigger page address, or 0 if the IRQ is not valid
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*/
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extern u64 ocxl_afu_irq_get_addr(struct ocxl_context *ctx, int irq_id);
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/**
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* Provide a callback to be called when an IRQ is triggered
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* @ctx: The AFU context that the IRQ is associated with
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* @irq_id: The IRQ ID
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* @handler: the callback to be called when the IRQ is triggered
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* @free_private: the callback to be called when the IRQ is freed (may be NULL)
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* @private: Private data to be passed to the callbacks
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*
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* Returns 0 on success, negative on failure
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*/
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int ocxl_irq_set_handler(struct ocxl_context *ctx, int irq_id,
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irqreturn_t (*handler)(void *private),
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void (*free_private)(void *private),
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void *private);
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// AFU Metadata
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/**
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* Get a pointer to the config for an AFU
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*
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* @afu: a pointer to the AFU to get the config for
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*
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* Returns a pointer to the AFU config
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*/
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struct ocxl_afu_config *ocxl_afu_config(struct ocxl_afu *afu);
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/**
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* Assign opaque hardware specific information to an OpenCAPI AFU.
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*
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* @dev: The PCI device associated with the OpenCAPI device
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* @private: the opaque hardware specific information to assign to the driver
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*/
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void ocxl_afu_set_private(struct ocxl_afu *afu, void *private);
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/**
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* Fetch the hardware specific information associated with an external OpenCAPI
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* AFU. This may be consumed by an external OpenCAPI driver.
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*
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* @afu: The AFU
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*
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* Returns the opaque pointer associated with the device, or NULL if not set
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*/
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void *ocxl_afu_get_private(struct ocxl_afu *dev);
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// Global MMIO
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/**
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* Read a 32 bit value from global MMIO
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @val: returns the value
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u32 *val);
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/**
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* Read a 64 bit value from global MMIO
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @val: returns the value
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u64 *val);
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/**
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* Write a 32 bit value to global MMIO
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @val: The value to write
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u32 val);
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/**
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* Write a 64 bit value to global MMIO
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @val: The value to write
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_write64(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u64 val);
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/**
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* Set bits in a 32 bit global MMIO register
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @mask: a mask of the bits to set
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_set32(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u32 mask);
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/**
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* Set bits in a 64 bit global MMIO register
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @mask: a mask of the bits to set
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_set64(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u64 mask);
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/**
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* Set bits in a 32 bit global MMIO register
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @mask: a mask of the bits to set
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_clear32(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u32 mask);
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/**
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* Set bits in a 64 bit global MMIO register
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*
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* @afu: The AFU
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* @offset: The Offset from the start of MMIO
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* @endian: the endianness that the MMIO data is in
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* @mask: a mask of the bits to set
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*
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* Returns 0 for success, negative on error
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*/
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int ocxl_global_mmio_clear64(struct ocxl_afu *afu, size_t offset,
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enum ocxl_endian endian, u64 mask);
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// Functions left here are for compatibility with the cxlflash driver
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/*
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* Read the configuration space of a function for the AFU specified by
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* the index 'afu_idx'. Fills in a ocxl_afu_config structure
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*/
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int ocxl_config_read_afu(struct pci_dev *dev,
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struct ocxl_fn_config *fn,
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struct ocxl_afu_config *afu,
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u8 afu_idx);
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/*
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* Tell an AFU, by writing in the configuration space, the PASIDs that
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* it can use. Range starts at 'pasid_base' and its size is a multiple
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* of 2
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*
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* 'afu_control_offset' is the offset of the AFU control DVSEC which
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* can be found in the function configuration
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*/
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void ocxl_config_set_afu_pasid(struct pci_dev *dev,
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int afu_control_offset,
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int pasid_base, u32 pasid_count_log);
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/*
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* Get the actag configuration for the function:
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* 'base' is the first actag value that can be used.
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* 'enabled' it the number of actags available, starting from base.
|
||
|
|
* 'supported' is the total number of actags desired by all the AFUs
|
||
|
|
* of the function.
|
||
|
|
*/
|
||
|
|
int ocxl_config_get_actag_info(struct pci_dev *dev,
|
||
|
|
u16 *base, u16 *enabled, u16 *supported);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Tell a function, by writing in the configuration space, the actags
|
||
|
|
* it can use.
|
||
|
|
*
|
||
|
|
* 'func_offset' is the offset of the Function DVSEC that can found in
|
||
|
|
* the function configuration
|
||
|
|
*/
|
||
|
|
void ocxl_config_set_actag(struct pci_dev *dev, int func_offset,
|
||
|
|
u32 actag_base, u32 actag_count);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Tell an AFU, by writing in the configuration space, the actags it
|
||
|
|
* can use.
|
||
|
|
*
|
||
|
|
* 'afu_control_offset' is the offset of the AFU control DVSEC for the
|
||
|
|
* desired AFU. It can be found in the AFU configuration
|
||
|
|
*/
|
||
|
|
void ocxl_config_set_afu_actag(struct pci_dev *dev,
|
||
|
|
int afu_control_offset,
|
||
|
|
int actag_base, int actag_count);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable/disable an AFU, by writing in the configuration space.
|
||
|
|
*
|
||
|
|
* 'afu_control_offset' is the offset of the AFU control DVSEC for the
|
||
|
|
* desired AFU. It can be found in the AFU configuration
|
||
|
|
*/
|
||
|
|
void ocxl_config_set_afu_state(struct pci_dev *dev,
|
||
|
|
int afu_control_offset, int enable);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set the Transaction Layer configuration in the configuration space.
|
||
|
|
* Only needed for function 0.
|
||
|
|
*
|
||
|
|
* It queries the host TL capabilities, find some common ground
|
||
|
|
* between the host and device, and set the Transaction Layer on both
|
||
|
|
* accordingly.
|
||
|
|
*/
|
||
|
|
int ocxl_config_set_TL(struct pci_dev *dev, int tl_dvsec);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Request an AFU to terminate a PASID.
|
||
|
|
* Will return once the AFU has acked the request, or an error in case
|
||
|
|
* of timeout.
|
||
|
|
*
|
||
|
|
* The hardware can only terminate one PASID at a time, so caller must
|
||
|
|
* guarantee some kind of serialization.
|
||
|
|
*
|
||
|
|
* 'afu_control_offset' is the offset of the AFU control DVSEC for the
|
||
|
|
* desired AFU. It can be found in the AFU configuration
|
||
|
|
*/
|
||
|
|
int ocxl_config_terminate_pasid(struct pci_dev *dev,
|
||
|
|
int afu_control_offset, int pasid);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Read the configuration space of a function and fill in a
|
||
|
|
* ocxl_fn_config structure with all the function details
|
||
|
|
*/
|
||
|
|
int ocxl_config_read_function(struct pci_dev *dev,
|
||
|
|
struct ocxl_fn_config *fn);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set up the opencapi link for the function.
|
||
|
|
*
|
||
|
|
* When called for the first time for a link, it sets up the Shared
|
||
|
|
* Process Area for the link and the interrupt handler to process
|
||
|
|
* translation faults.
|
||
|
|
*
|
||
|
|
* Returns a 'link handle' that should be used for further calls for
|
||
|
|
* the link
|
||
|
|
*/
|
||
|
|
int ocxl_link_setup(struct pci_dev *dev, int PE_mask,
|
||
|
|
void **link_handle);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Remove the association between the function and its link.
|
||
|
|
*/
|
||
|
|
void ocxl_link_release(struct pci_dev *dev, void *link_handle);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Add a Process Element to the Shared Process Area for a link.
|
||
|
|
* The process is defined by its PASID, pid, tid and its mm_struct.
|
||
|
|
*
|
||
|
|
* 'xsl_err_cb' is an optional callback if the driver wants to be
|
||
|
|
* notified when the translation fault interrupt handler detects an
|
||
|
|
* address error.
|
||
|
|
* 'xsl_err_data' is an argument passed to the above callback, if
|
||
|
|
* defined
|
||
|
|
*/
|
||
|
|
int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
|
||
|
|
u64 amr, struct mm_struct *mm,
|
||
|
|
void (*xsl_err_cb)(void *data, u64 addr, u64 dsisr),
|
||
|
|
void *xsl_err_data);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Remove a Process Element from the Shared Process Area for a link
|
||
|
|
*/
|
||
|
|
int ocxl_link_remove_pe(void *link_handle, int pasid);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Allocate an AFU interrupt associated to the link.
|
||
|
|
*
|
||
|
|
* 'hw_irq' is the hardware interrupt number
|
||
|
|
* 'obj_handle' is the 64-bit object handle to be passed to the AFU to
|
||
|
|
* trigger the interrupt.
|
||
|
|
* On P9, 'obj_handle' is an address, which, if written, triggers the
|
||
|
|
* interrupt. It is an MMIO address which needs to be remapped (one
|
||
|
|
* page).
|
||
|
|
*/
|
||
|
|
int ocxl_link_irq_alloc(void *link_handle, int *hw_irq,
|
||
|
|
u64 *obj_handle);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Free a previously allocated AFU interrupt
|
||
|
|
*/
|
||
|
|
void ocxl_link_free_irq(void *link_handle, int hw_irq);
|
||
|
|
|
||
|
|
#endif /* _MISC_OCXL_H_ */
|