220 lines
6.1 KiB
C
220 lines
6.1 KiB
C
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/**
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* Copyright (c) 2017 Redpine Signals Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __RSI_HAL_H__
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#define __RSI_HAL_H__
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/* Device Operating modes */
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#define DEV_OPMODE_WIFI_ALONE 1
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#define DEV_OPMODE_BT_ALONE 4
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#define DEV_OPMODE_BT_LE_ALONE 8
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#define DEV_OPMODE_BT_DUAL 12
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#define DEV_OPMODE_STA_BT 5
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#define DEV_OPMODE_STA_BT_LE 9
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#define DEV_OPMODE_STA_BT_DUAL 13
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#define DEV_OPMODE_AP_BT 6
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#define DEV_OPMODE_AP_BT_DUAL 14
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#define FLASH_WRITE_CHUNK_SIZE (4 * 1024)
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#define FLASH_SECTOR_SIZE (4 * 1024)
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#define FLASH_SIZE_ADDR 0x04000016
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#define PING_BUFFER_ADDRESS 0x19000
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#define PONG_BUFFER_ADDRESS 0x1a000
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#define SWBL_REGIN 0x41050034
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#define SWBL_REGOUT 0x4105003c
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#define PING_WRITE 0x1
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#define PONG_WRITE 0x2
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#define BL_CMD_TIMEOUT 2000
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#define BL_BURN_TIMEOUT (50 * 1000)
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#define REGIN_VALID 0xA
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#define REGIN_INPUT 0xA0
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#define REGOUT_VALID 0xAB
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#define REGOUT_INVALID (~0xAB)
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#define CMD_PASS 0xAA
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#define CMD_FAIL 0xCC
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#define LOAD_HOSTED_FW 'A'
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#define BURN_HOSTED_FW 'B'
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#define PING_VALID 'I'
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#define PONG_VALID 'O'
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#define PING_AVAIL 'I'
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#define PONG_AVAIL 'O'
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#define EOF_REACHED 'E'
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#define CHECK_CRC 'K'
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#define POLLING_MODE 'P'
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#define CONFIG_AUTO_READ_MODE 'R'
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#define JUMP_TO_ZERO_PC 'J'
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#define FW_LOADING_SUCCESSFUL 'S'
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#define LOADING_INITIATED '1'
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#define RSI_ULP_RESET_REG 0x161
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#define RSI_WATCH_DOG_TIMER_1 0x16c
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#define RSI_WATCH_DOG_TIMER_2 0x16d
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#define RSI_WATCH_DOG_DELAY_TIMER_1 0x16e
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#define RSI_WATCH_DOG_DELAY_TIMER_2 0x16f
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#define RSI_WATCH_DOG_TIMER_ENABLE 0x170
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/* Watchdog timer addresses for 9116 */
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#define NWP_AHB_BASE_ADDR 0x41300000
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#define NWP_WWD_INTERRUPT_TIMER (NWP_AHB_BASE_ADDR + 0x300)
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#define NWP_WWD_SYSTEM_RESET_TIMER (NWP_AHB_BASE_ADDR + 0x304)
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#define NWP_WWD_WINDOW_TIMER (NWP_AHB_BASE_ADDR + 0x308)
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#define NWP_WWD_TIMER_SETTINGS (NWP_AHB_BASE_ADDR + 0x30C)
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#define NWP_WWD_MODE_AND_RSTART (NWP_AHB_BASE_ADDR + 0x310)
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#define NWP_WWD_RESET_BYPASS (NWP_AHB_BASE_ADDR + 0x314)
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#define NWP_FSM_INTR_MASK_REG (NWP_AHB_BASE_ADDR + 0x104)
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/* Watchdog timer values */
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#define NWP_WWD_INT_TIMER_CLKS 5
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#define NWP_WWD_SYS_RESET_TIMER_CLKS 4
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#define NWP_WWD_TIMER_DISABLE 0xAA0001
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#define RSI_ULP_WRITE_0 00
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#define RSI_ULP_WRITE_2 02
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#define RSI_ULP_WRITE_50 50
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#define RSI_RESTART_WDT BIT(11)
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#define RSI_BYPASS_ULP_ON_WDT BIT(1)
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#define RSI_ULP_TIMER_ENABLE ((0xaa000) | RSI_RESTART_WDT | \
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RSI_BYPASS_ULP_ON_WDT)
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#define RSI_RF_SPI_PROG_REG_BASE_ADDR 0x40080000
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#define RSI_GSPI_CTRL_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR)
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#define RSI_GSPI_CTRL_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
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#define RSI_GSPI_DATA_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
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#define RSI_GSPI_DATA_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
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#define RSI_GSPI_DATA_REG2 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
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#define RSI_GSPI_CTRL_REG0_VALUE 0x340
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#define RSI_GSPI_DMA_MODE BIT(13)
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#define RSI_GSPI_2_ULP BIT(12)
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#define RSI_GSPI_TRIG BIT(7)
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#define RSI_GSPI_READ BIT(6)
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#define RSI_GSPI_RF_SPI_ACTIVE BIT(8)
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/* Boot loader commands */
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#define SEND_RPS_FILE '2'
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#define FW_IMAGE_MIN_ADDRESS (68 * 1024)
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#define MAX_FLASH_FILE_SIZE (400 * 1024) //400K
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#define FLASH_START_ADDRESS 16
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#define COMMON_HAL_CARD_READY_IND 0x0
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#define COMMAN_HAL_WAIT_FOR_CARD_READY 1
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#define RSI_DEV_OPMODE_WIFI_ALONE 1
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#define RSI_DEV_COEX_MODE_WIFI_ALONE 1
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#define BBP_INFO_40MHZ 0x6
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#define FW_FLASH_OFFSET 0x820
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#define LMAC_VER_OFFSET_9113 (FW_FLASH_OFFSET + 0x200)
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#define LMAC_VER_OFFSET_9116 0x22C2
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#define MAX_DWORD_ALIGN_BYTES 64
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#define RSI_COMMON_REG_SIZE 2
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#define RSI_9116_REG_SIZE 4
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#define FW_ALIGN_SIZE 4
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#define RSI_9116_FW_MAGIC_WORD 0x5aa5
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#define MEM_ACCESS_CTRL_FROM_HOST 0x41300000
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#define RAM_384K_ACCESS_FROM_TA (BIT(2) | BIT(3) | BIT(4) | BIT(5) | \
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BIT(20) | BIT(21) | BIT(22) | \
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BIT(23) | BIT(24) | BIT(25))
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struct bl_header {
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__le32 flags;
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__le32 image_no;
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__le32 check_sum;
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__le32 flash_start_address;
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__le32 flash_len;
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} __packed;
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struct ta_metadata {
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char *name;
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unsigned int address;
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};
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#define RSI_BL_CTRL_LEN_MASK 0xFFFFFF
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#define RSI_BL_CTRL_SPI_32BIT_MODE BIT(27)
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#define RSI_BL_CTRL_REL_TA_SOFTRESET BIT(28)
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#define RSI_BL_CTRL_START_FROM_ROM_PC BIT(29)
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#define RSI_BL_CTRL_SPI_8BIT_MODE BIT(30)
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#define RSI_BL_CTRL_LAST_ENTRY BIT(31)
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struct bootload_entry {
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__le32 control;
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__le32 dst_addr;
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} __packed;
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struct bootload_ds {
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__le16 fixed_pattern;
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__le16 offset;
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__le32 reserved;
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struct bootload_entry bl_entry[7];
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} __packed;
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struct rsi_mgmt_desc {
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__le16 len_qno;
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u8 frame_type;
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u8 misc_flags;
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u8 xtend_desc_size;
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u8 header_len;
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__le16 frame_info;
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__le16 rate_info;
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__le16 bbp_info;
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__le16 seq_ctrl;
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u8 reserved2;
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u8 sta_id;
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} __packed;
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struct rsi_data_desc {
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__le16 len_qno;
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u8 cfm_frame_type;
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u8 misc_flags;
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u8 xtend_desc_size;
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u8 header_len;
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__le16 frame_info;
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__le16 rate_info;
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__le16 bbp_info;
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__le16 mac_flags;
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u8 qid_tid;
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u8 sta_id;
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} __packed;
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struct rsi_bt_desc {
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__le16 len_qno;
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__le16 reserved1;
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__le32 reserved2;
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__le32 reserved3;
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__le16 reserved4;
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__le16 bt_pkt_type;
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} __packed;
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int rsi_hal_device_init(struct rsi_hw *adapter);
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int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
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int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
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int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
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int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
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int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
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#endif
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