351 lines
7.9 KiB
C
351 lines
7.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2009-2012 Realtek Corporation.*/
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#ifndef __REALTEK_FIRMWARE92S_H__
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#define __REALTEK_FIRMWARE92S_H__
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#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
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#define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE 90000
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#define RTL8190_CPU_START_OFFSET 0x80
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/* Firmware Local buffer size. 64k */
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#define MAX_FIRMWARE_CODE_SIZE 0xFF00
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#define RT_8192S_FIRMWARE_HDR_SIZE 80
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#define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32
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/* support till 64 bit bus width OS */
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#define MAX_DEV_ADDR_SIZE 8
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#define MAX_FIRMWARE_INFORMATION_SIZE 32
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#define MAX_802_11_HEADER_LENGTH (40 + \
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MAX_FIRMWARE_INFORMATION_SIZE)
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#define ENCRYPTION_MAX_OVERHEAD 128
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#define MAX_FRAGMENT_COUNT 8
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#define MAX_TRANSMIT_BUFFER_SIZE (1600 + \
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(MAX_802_11_HEADER_LENGTH + \
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ENCRYPTION_MAX_OVERHEAD) *\
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MAX_FRAGMENT_COUNT)
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#define H2C_TX_CMD_HDR_LEN 8
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/* The following DM control code are for Reg0x364, */
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#define FW_DIG_ENABLE_CTL BIT(0)
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#define FW_HIGH_PWR_ENABLE_CTL BIT(1)
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#define FW_SS_CTL BIT(2)
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#define FW_RA_INIT_CTL BIT(3)
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#define FW_RA_BG_CTL BIT(4)
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#define FW_RA_N_CTL BIT(5)
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#define FW_PWR_TRK_CTL BIT(6)
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#define FW_IQK_CTL BIT(7)
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#define FW_FA_CTL BIT(8)
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#define FW_DRIVER_CTRL_DM_CTL BIT(9)
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#define FW_PAPE_CTL_BY_SW_HW BIT(10)
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#define FW_DISABLE_ALL_DM 0
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#define FW_PWR_TRK_PARAM_CLR 0x0000ffff
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#define FW_RA_PARAM_CLR 0xffff0000
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enum desc_packet_type {
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DESC_PACKET_TYPE_INIT = 0,
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DESC_PACKET_TYPE_NORMAL = 1,
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};
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/* 8-bytes alignment required */
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struct fw_priv {
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/* --- long word 0 ---- */
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/* 0x12: CE product, 0x92: IT product */
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u8 signature_0;
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/* 0x87: CE product, 0x81: IT product */
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u8 signature_1;
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/* 0x81: PCI-AP, 01:PCIe, 02: 92S-U,
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* 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */
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u8 hci_sel;
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/* the same value as reigster value */
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u8 chip_version;
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/* customer ID low byte */
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u8 customer_id_0;
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/* customer ID high byte */
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u8 customer_id_1;
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/* 0x11: 1T1R, 0x12: 1T2R,
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* 0x92: 1T2R turbo, 0x22: 2T2R */
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u8 rf_config;
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/* 4: 4EP, 6: 6EP, 11: 11EP */
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u8 usb_ep_num;
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/* --- long word 1 ---- */
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/* regulatory class bit map 0 */
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u8 regulatory_class_0;
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/* regulatory class bit map 1 */
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u8 regulatory_class_1;
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/* regulatory class bit map 2 */
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u8 regulatory_class_2;
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/* regulatory class bit map 3 */
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u8 regulatory_class_3;
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/* 0:SWSI, 1:HWSI, 2:HWPI */
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u8 rfintfs;
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u8 def_nettype;
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u8 rsvd010;
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u8 rsvd011;
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/* --- long word 2 ---- */
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/* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */
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u8 lbk_mode;
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/* 1: for MP use, 0: for normal
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* driver (to be discussed) */
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u8 mp_mode;
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u8 rsvd020;
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u8 rsvd021;
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u8 rsvd022;
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u8 rsvd023;
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u8 rsvd024;
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u8 rsvd025;
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/* --- long word 3 ---- */
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/* QoS enable */
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u8 qos_en;
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/* 40MHz BW enable */
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/* 4181 convert AMSDU to AMPDU, 0: disable */
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u8 bw_40mhz_en;
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u8 amsdu2ampdu_en;
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/* 11n AMPDU enable */
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u8 ampdu_en;
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/* FW offloads, 0: driver handles */
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u8 rate_control_offload;
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/* FW offloads, 0: driver handles */
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u8 aggregation_offload;
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u8 rsvd030;
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u8 rsvd031;
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/* --- long word 4 ---- */
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/* 1. FW offloads, 0: driver handles */
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u8 beacon_offload;
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/* 2. FW offloads, 0: driver handles */
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u8 mlme_offload;
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/* 3. FW offloads, 0: driver handles */
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u8 hwpc_offload;
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/* 4. FW offloads, 0: driver handles */
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u8 tcp_checksum_offload;
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/* 5. FW offloads, 0: driver handles */
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u8 tcp_offload;
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/* 6. FW offloads, 0: driver handles */
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u8 ps_control_offload;
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/* 7. FW offloads, 0: driver handles */
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u8 wwlan_offload;
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u8 rsvd040;
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/* --- long word 5 ---- */
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/* tcp tx packet length low byte */
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u8 tcp_tx_frame_len_L;
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/* tcp tx packet length high byte */
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u8 tcp_tx_frame_len_H;
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/* tcp rx packet length low byte */
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u8 tcp_rx_frame_len_L;
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/* tcp rx packet length high byte */
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u8 tcp_rx_frame_len_H;
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u8 rsvd050;
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u8 rsvd051;
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u8 rsvd052;
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u8 rsvd053;
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};
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/* 8-byte alinment required */
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struct fw_hdr {
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/* --- LONG WORD 0 ---- */
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u16 signature;
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/* 0x8000 ~ 0x8FFF for FPGA version,
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* 0x0000 ~ 0x7FFF for ASIC version, */
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u16 version;
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/* define the size of boot loader */
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u32 dmem_size;
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/* --- LONG WORD 1 ---- */
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/* define the size of FW in IMEM */
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u32 img_imem_size;
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/* define the size of FW in SRAM */
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u32 img_sram_size;
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/* --- LONG WORD 2 ---- */
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/* define the size of DMEM variable */
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u32 fw_priv_size;
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u32 rsvd0;
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/* --- LONG WORD 3 ---- */
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u32 rsvd1;
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u32 rsvd2;
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struct fw_priv fwpriv;
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} ;
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enum fw_status {
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FW_STATUS_INIT = 0,
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FW_STATUS_LOAD_IMEM = 1,
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FW_STATUS_LOAD_EMEM = 2,
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FW_STATUS_LOAD_DMEM = 3,
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FW_STATUS_READY = 4,
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};
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struct rt_firmware {
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struct fw_hdr *pfwheader;
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enum fw_status fwstatus;
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u16 firmwareversion;
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u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
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u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE];
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u32 fw_imem_len;
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u32 fw_emem_len;
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u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE];
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u32 sz_fw_tmpbufferlen;
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u16 cmdpacket_fragthresold;
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};
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struct h2c_set_pwrmode_parm {
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u8 mode;
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u8 flag_low_traffic_en;
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u8 flag_lpnav_en;
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u8 flag_rf_low_snr_en;
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/* 1: dps, 0: 32k */
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u8 flag_dps_en;
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u8 bcn_rx_en;
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u8 bcn_pass_cnt;
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/* beacon TO (ms). ¡§=0¡¨ no limit. */
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u8 bcn_to;
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u16 bcn_itv;
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/* only for VOIP mode. */
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u8 app_itv;
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u8 awake_bcn_itvl;
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u8 smart_ps;
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/* unit: 100 ms */
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u8 bcn_pass_period;
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};
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struct h2c_joinbss_rpt_parm {
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u8 opmode;
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u8 ps_qos_info;
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u8 bssid[6];
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u16 bcnitv;
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u16 aid;
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} ;
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struct h2c_wpa_ptk {
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/* EAPOL-Key Key Confirmation Key (KCK) */
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u8 kck[16];
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/* EAPOL-Key Key Encryption Key (KEK) */
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u8 kek[16];
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/* Temporal Key 1 (TK1) */
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u8 tk1[16];
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union {
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/* Temporal Key 2 (TK2) */
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u8 tk2[16];
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struct {
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u8 tx_mic_key[8];
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u8 rx_mic_key[8];
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} athu;
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} u;
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};
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struct h2c_wpa_two_way_parm {
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/* algorithm TKIP or AES */
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u8 pairwise_en_alg;
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u8 group_en_alg;
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struct h2c_wpa_ptk wpa_ptk_value;
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} ;
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enum h2c_cmd {
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FW_H2C_SETPWRMODE = 0,
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FW_H2C_JOINBSSRPT = 1,
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FW_H2C_WOWLAN_UPDATE_GTK = 2,
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FW_H2C_WOWLAN_UPDATE_IV = 3,
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FW_H2C_WOWLAN_OFFLOAD = 4,
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};
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enum fw_h2c_cmd {
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H2C_READ_MACREG_CMD, /*0*/
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H2C_WRITE_MACREG_CMD,
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H2C_READBB_CMD,
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H2C_WRITEBB_CMD,
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H2C_READRF_CMD,
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H2C_WRITERF_CMD, /*5*/
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H2C_READ_EEPROM_CMD,
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H2C_WRITE_EEPROM_CMD,
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H2C_READ_EFUSE_CMD,
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H2C_WRITE_EFUSE_CMD,
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H2C_READ_CAM_CMD, /*10*/
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H2C_WRITE_CAM_CMD,
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H2C_SETBCNITV_CMD,
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H2C_SETMBIDCFG_CMD,
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H2C_JOINBSS_CMD,
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H2C_DISCONNECT_CMD, /*15*/
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H2C_CREATEBSS_CMD,
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H2C_SETOPMODE_CMD,
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H2C_SITESURVEY_CMD,
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H2C_SETAUTH_CMD,
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H2C_SETKEY_CMD, /*20*/
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H2C_SETSTAKEY_CMD,
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H2C_SETASSOCSTA_CMD,
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H2C_DELASSOCSTA_CMD,
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H2C_SETSTAPWRSTATE_CMD,
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H2C_SETBASICRATE_CMD, /*25*/
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H2C_GETBASICRATE_CMD,
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H2C_SETDATARATE_CMD,
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H2C_GETDATARATE_CMD,
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H2C_SETPHYINFO_CMD,
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H2C_GETPHYINFO_CMD, /*30*/
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H2C_SETPHY_CMD,
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H2C_GETPHY_CMD,
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H2C_READRSSI_CMD,
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H2C_READGAIN_CMD,
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H2C_SETATIM_CMD, /*35*/
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H2C_SETPWRMODE_CMD,
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H2C_JOINBSSRPT_CMD,
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H2C_SETRATABLE_CMD,
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H2C_GETRATABLE_CMD,
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H2C_GETCCXREPORT_CMD, /*40*/
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H2C_GETDTMREPORT_CMD,
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H2C_GETTXRATESTATICS_CMD,
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H2C_SETUSBSUSPEND_CMD,
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H2C_SETH2CLBK_CMD,
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H2C_TMP1, /*45*/
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H2C_WOWLAN_UPDATE_GTK_CMD,
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H2C_WOWLAN_FW_OFFLOAD,
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H2C_TMP2,
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H2C_TMP3,
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H2C_WOWLAN_UPDATE_IV_CMD, /*50*/
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H2C_TMP4,
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};
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/* The following macros are used for FW
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* CMD map and parameter updated. */
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#define FW_CMD_IO_CLR(rtlpriv, _bit) \
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do { \
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udelay(1000); \
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rtlpriv->rtlhal.fwcmd_iomap &= (~_bit); \
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} while (0)
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#define FW_CMD_IO_UPDATE(rtlpriv, _val) \
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rtlpriv->rtlhal.fwcmd_iomap = _val;
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#define FW_CMD_IO_SET(rtlpriv, _val) \
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do { \
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rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \
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FW_CMD_IO_UPDATE(rtlpriv, _val); \
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} while (0)
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#define FW_CMD_PARA_SET(rtlpriv, _val) \
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do { \
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rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \
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rtlpriv->rtlhal.fwcmd_ioparam = _val; \
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} while (0)
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#define FW_CMD_IO_QUERY(rtlpriv) \
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(u16)(rtlpriv->rtlhal.fwcmd_iomap)
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#define FW_CMD_IO_PARA_QUERY(rtlpriv) \
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((u32)(rtlpriv->rtlhal.fwcmd_ioparam))
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int rtl92s_download_fw(struct ieee80211_hw *hw);
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void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
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void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
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u8 mstatus, u8 ps_qosinfo);
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#endif
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