404 lines
9.0 KiB
C
404 lines
9.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* NXP TJA1100 BroadRReach PHY driver
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*
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* Copyright (C) 2018 Marek Vasut <marex@denx.de>
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*/
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#include <linux/delay.h>
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#include <linux/ethtool.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/hwmon.h>
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#include <linux/bitfield.h>
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#define PHY_ID_MASK 0xfffffff0
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#define PHY_ID_TJA1100 0x0180dc40
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#define PHY_ID_TJA1101 0x0180dd00
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#define MII_ECTRL 17
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#define MII_ECTRL_LINK_CONTROL BIT(15)
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#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
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#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
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#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
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#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
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#define MII_ECTRL_CONFIG_EN BIT(2)
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#define MII_ECTRL_WAKE_REQUEST BIT(0)
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#define MII_CFG1 18
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#define MII_CFG1_AUTO_OP BIT(14)
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#define MII_CFG1_SLEEP_CONFIRM BIT(6)
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#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
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#define MII_CFG1_LED_MODE_LINKUP 0
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#define MII_CFG1_LED_ENABLE BIT(3)
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#define MII_CFG2 19
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#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
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#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
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#define MII_INTSRC 21
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#define MII_INTSRC_TEMP_ERR BIT(1)
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#define MII_INTSRC_UV_ERR BIT(3)
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#define MII_COMMSTAT 23
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#define MII_COMMSTAT_LINK_UP BIT(15)
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#define MII_GENSTAT 24
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#define MII_GENSTAT_PLL_LOCKED BIT(14)
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#define MII_COMMCFG 27
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#define MII_COMMCFG_AUTO_OP BIT(15)
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struct tja11xx_priv {
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char *hwmon_name;
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struct device *hwmon_dev;
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};
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struct tja11xx_phy_stats {
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const char *string;
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u8 reg;
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u8 off;
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u16 mask;
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};
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static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
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{ "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
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{ "phy_polarity_detect", 25, 6, BIT(6) },
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{ "phy_open_detect", 25, 7, BIT(7) },
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{ "phy_short_detect", 25, 8, BIT(8) },
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{ "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
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{ "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
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};
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static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
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{
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int i, ret;
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for (i = 0; i < 200; i++) {
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ret = phy_read(phydev, reg);
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if (ret < 0)
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return ret;
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if ((ret & mask) == set)
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return 0;
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usleep_range(100, 150);
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}
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return -ETIMEDOUT;
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}
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static int phy_modify_check(struct phy_device *phydev, u8 reg,
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u16 mask, u16 set)
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{
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int ret;
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ret = phy_modify(phydev, reg, mask, set);
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if (ret)
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return ret;
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return tja11xx_check(phydev, reg, mask, set);
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}
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static int tja11xx_enable_reg_write(struct phy_device *phydev)
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{
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return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
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}
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static int tja11xx_enable_link_control(struct phy_device *phydev)
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{
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return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
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}
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static int tja11xx_wakeup(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read(phydev, MII_ECTRL);
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if (ret < 0)
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return ret;
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switch (ret & MII_ECTRL_POWER_MODE_MASK) {
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case MII_ECTRL_POWER_MODE_NO_CHANGE:
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break;
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case MII_ECTRL_POWER_MODE_NORMAL:
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ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
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if (ret)
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return ret;
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ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
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if (ret)
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return ret;
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break;
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case MII_ECTRL_POWER_MODE_STANDBY:
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ret = phy_modify_check(phydev, MII_ECTRL,
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MII_ECTRL_POWER_MODE_MASK,
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MII_ECTRL_POWER_MODE_STANDBY);
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if (ret)
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return ret;
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ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
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MII_ECTRL_POWER_MODE_NORMAL);
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if (ret)
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return ret;
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ret = phy_modify_check(phydev, MII_GENSTAT,
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MII_GENSTAT_PLL_LOCKED,
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MII_GENSTAT_PLL_LOCKED);
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if (ret)
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return ret;
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return tja11xx_enable_link_control(phydev);
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default:
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break;
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}
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return 0;
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}
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static int tja11xx_soft_reset(struct phy_device *phydev)
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{
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int ret;
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ret = tja11xx_enable_reg_write(phydev);
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if (ret)
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return ret;
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return genphy_soft_reset(phydev);
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}
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static int tja11xx_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = tja11xx_enable_reg_write(phydev);
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if (ret)
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return ret;
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->speed = SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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switch (phydev->phy_id & PHY_ID_MASK) {
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case PHY_ID_TJA1100:
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ret = phy_modify(phydev, MII_CFG1,
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MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
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MII_CFG1_LED_ENABLE,
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MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
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MII_CFG1_LED_ENABLE);
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if (ret)
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return ret;
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break;
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case PHY_ID_TJA1101:
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ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
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if (ret)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
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if (ret)
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return ret;
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ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
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MII_CFG2_SLEEP_REQUEST_TO_16MS);
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if (ret)
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return ret;
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ret = tja11xx_wakeup(phydev);
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if (ret < 0)
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return ret;
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/* ACK interrupts by reading the status register */
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ret = phy_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int tja11xx_read_status(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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if (phydev->link) {
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ret = phy_read(phydev, MII_COMMSTAT);
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if (ret < 0)
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return ret;
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if (!(ret & MII_COMMSTAT_LINK_UP))
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phydev->link = 0;
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}
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return 0;
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}
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static int tja11xx_get_sset_count(struct phy_device *phydev)
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{
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return ARRAY_SIZE(tja11xx_hw_stats);
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}
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static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
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strncpy(data + i * ETH_GSTRING_LEN,
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tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
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}
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}
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static void tja11xx_get_stats(struct phy_device *phydev,
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struct ethtool_stats *stats, u64 *data)
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{
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
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ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
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if (ret < 0)
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data[i] = U64_MAX;
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else {
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data[i] = ret & tja11xx_hw_stats[i].mask;
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data[i] >>= tja11xx_hw_stats[i].off;
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}
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}
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}
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static int tja11xx_hwmon_read(struct device *dev,
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enum hwmon_sensor_types type,
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u32 attr, int channel, long *value)
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{
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struct phy_device *phydev = dev_get_drvdata(dev);
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int ret;
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if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
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ret = phy_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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*value = !!(ret & MII_INTSRC_TEMP_ERR);
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return 0;
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}
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if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
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ret = phy_read(phydev, MII_INTSRC);
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if (ret < 0)
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return ret;
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*value = !!(ret & MII_INTSRC_UV_ERR);
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return 0;
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}
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return -EOPNOTSUPP;
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}
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static umode_t tja11xx_hwmon_is_visible(const void *data,
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enum hwmon_sensor_types type,
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u32 attr, int channel)
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{
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if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
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return 0444;
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if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
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return 0444;
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return 0;
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}
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static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
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HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
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HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
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NULL
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};
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static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
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.is_visible = tja11xx_hwmon_is_visible,
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.read = tja11xx_hwmon_read,
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};
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static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
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.ops = &tja11xx_hwmon_hwmon_ops,
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.info = tja11xx_hwmon_info,
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};
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static int tja11xx_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct tja11xx_priv *priv;
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int i;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
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if (!priv->hwmon_name)
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return -ENOMEM;
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for (i = 0; priv->hwmon_name[i]; i++)
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if (hwmon_is_bad_char(priv->hwmon_name[i]))
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priv->hwmon_name[i] = '_';
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priv->hwmon_dev =
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devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
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phydev,
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&tja11xx_hwmon_chip_info,
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NULL);
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return PTR_ERR_OR_ZERO(priv->hwmon_dev);
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}
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static struct phy_driver tja11xx_driver[] = {
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{
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PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
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.name = "NXP TJA1100",
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.features = PHY_BASIC_T1_FEATURES,
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.probe = tja11xx_probe,
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.soft_reset = tja11xx_soft_reset,
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.config_init = tja11xx_config_init,
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.read_status = tja11xx_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.set_loopback = genphy_loopback,
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/* Statistics */
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.get_sset_count = tja11xx_get_sset_count,
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.get_strings = tja11xx_get_strings,
|
||
|
|
.get_stats = tja11xx_get_stats,
|
||
|
|
}, {
|
||
|
|
PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
|
||
|
|
.name = "NXP TJA1101",
|
||
|
|
.features = PHY_BASIC_T1_FEATURES,
|
||
|
|
.probe = tja11xx_probe,
|
||
|
|
.soft_reset = tja11xx_soft_reset,
|
||
|
|
.config_init = tja11xx_config_init,
|
||
|
|
.read_status = tja11xx_read_status,
|
||
|
|
.suspend = genphy_suspend,
|
||
|
|
.resume = genphy_resume,
|
||
|
|
.set_loopback = genphy_loopback,
|
||
|
|
/* Statistics */
|
||
|
|
.get_sset_count = tja11xx_get_sset_count,
|
||
|
|
.get_strings = tja11xx_get_strings,
|
||
|
|
.get_stats = tja11xx_get_stats,
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
module_phy_driver(tja11xx_driver);
|
||
|
|
|
||
|
|
static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
|
||
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
|
||
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
|
||
|
|
{ }
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
||
|
|
MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
|
||
|
|
MODULE_LICENSE("GPL");
|