228 lines
8.5 KiB
C
228 lines
8.5 KiB
C
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/*
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* QLogic qlcnic NIC Driver
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* Copyright (c) 2009-2013 QLogic Corporation
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*
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* See LICENSE.qlcnic for copyright and licensing details.
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*/
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#ifndef __QLCNIC_HW_H
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#define __QLCNIC_HW_H
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/* Common registers in 83xx and 82xx */
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enum qlcnic_regs {
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QLCNIC_PEG_HALT_STATUS1 = 0,
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QLCNIC_PEG_HALT_STATUS2,
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QLCNIC_PEG_ALIVE_COUNTER,
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QLCNIC_FLASH_LOCK_OWNER,
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QLCNIC_FW_CAPABILITIES,
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QLCNIC_CRB_DRV_ACTIVE,
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QLCNIC_CRB_DEV_STATE,
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QLCNIC_CRB_DRV_STATE,
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QLCNIC_CRB_DRV_SCRATCH,
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QLCNIC_CRB_DEV_PARTITION_INFO,
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QLCNIC_CRB_DRV_IDC_VER,
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QLCNIC_FW_VERSION_MAJOR,
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QLCNIC_FW_VERSION_MINOR,
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QLCNIC_FW_VERSION_SUB,
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QLCNIC_CRB_DEV_NPAR_STATE,
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QLCNIC_FW_IMG_VALID,
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QLCNIC_CMDPEG_STATE,
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QLCNIC_RCVPEG_STATE,
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QLCNIC_ASIC_TEMP,
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QLCNIC_FW_API,
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QLCNIC_DRV_OP_MODE,
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QLCNIC_FLASH_LOCK,
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QLCNIC_FLASH_UNLOCK,
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};
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/* Read from an address offset from BAR0, existing registers */
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#define QLC_SHARED_REG_RD32(a, addr) \
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readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
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/* Write to an address offset from BAR0, existing registers */
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#define QLC_SHARED_REG_WR32(a, addr, value) \
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writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
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/* Read from a direct address offset from BAR0, additional registers */
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#define QLCRDX(ahw, addr) \
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readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))
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/* Write to a direct address offset from BAR0, additional registers */
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#define QLCWRX(ahw, addr, value) \
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writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))
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#define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1
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#define QLCNIC_CMD_CONFIG_INTRPT 0x2
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#define QLCNIC_CMD_CREATE_RX_CTX 0x7
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#define QLCNIC_CMD_DESTROY_RX_CTX 0x8
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#define QLCNIC_CMD_CREATE_TX_CTX 0x9
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#define QLCNIC_CMD_DESTROY_TX_CTX 0xa
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#define QLCNIC_CMD_CONFIGURE_LRO 0xC
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#define QLCNIC_CMD_CONFIGURE_MAC_LEARNING 0xD
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#define QLCNIC_CMD_GET_STATISTICS 0xF
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#define QLCNIC_CMD_INTRPT_TEST 0x11
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#define QLCNIC_CMD_SET_MTU 0x12
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#define QLCNIC_CMD_READ_PHY 0x13
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#define QLCNIC_CMD_WRITE_PHY 0x14
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#define QLCNIC_CMD_READ_HW_REG 0x15
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#define QLCNIC_CMD_GET_FLOW_CTL 0x16
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#define QLCNIC_CMD_SET_FLOW_CTL 0x17
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#define QLCNIC_CMD_READ_MAX_MTU 0x18
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#define QLCNIC_CMD_READ_MAX_LRO 0x19
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#define QLCNIC_CMD_MAC_ADDRESS 0x1f
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#define QLCNIC_CMD_GET_PCI_INFO 0x20
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#define QLCNIC_CMD_GET_NIC_INFO 0x21
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#define QLCNIC_CMD_SET_NIC_INFO 0x22
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#define QLCNIC_CMD_GET_ESWITCH_CAPABILITY 0x24
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#define QLCNIC_CMD_TOGGLE_ESWITCH 0x25
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#define QLCNIC_CMD_GET_ESWITCH_STATUS 0x26
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#define QLCNIC_CMD_SET_PORTMIRRORING 0x27
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#define QLCNIC_CMD_CONFIGURE_ESWITCH 0x28
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#define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG 0x29
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#define QLCNIC_CMD_GET_ESWITCH_STATS 0x2a
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#define QLCNIC_CMD_CONFIG_PORT 0x2e
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#define QLCNIC_CMD_TEMP_SIZE 0x2f
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#define QLCNIC_CMD_GET_TEMP_HDR 0x30
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#define QLCNIC_CMD_BC_EVENT_SETUP 0x31
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#define QLCNIC_CMD_CONFIG_VPORT 0x32
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#define QLCNIC_CMD_DCB_QUERY_CAP 0x34
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#define QLCNIC_CMD_DCB_QUERY_PARAM 0x35
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#define QLCNIC_CMD_GET_MAC_STATS 0x37
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#define QLCNIC_CMD_82XX_SET_DRV_VER 0x38
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#define QLCNIC_CMD_MQ_TX_CONFIG_INTR 0x39
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#define QLCNIC_CMD_GET_LED_STATUS 0x3C
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#define QLCNIC_CMD_CONFIGURE_RSS 0x41
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#define QLCNIC_CMD_CONFIG_INTR_COAL 0x43
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#define QLCNIC_CMD_CONFIGURE_LED 0x44
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#define QLCNIC_CMD_CONFIG_MAC_VLAN 0x45
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#define QLCNIC_CMD_GET_LINK_EVENT 0x48
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#define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE 0x49
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#define QLCNIC_CMD_CONFIGURE_HW_LRO 0x4A
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#define QLCNIC_CMD_SET_INGRESS_ENCAP 0x4E
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#define QLCNIC_CMD_INIT_NIC_FUNC 0x60
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#define QLCNIC_CMD_STOP_NIC_FUNC 0x61
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#define QLCNIC_CMD_IDC_ACK 0x63
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#define QLCNIC_CMD_SET_PORT_CONFIG 0x66
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#define QLCNIC_CMD_GET_PORT_CONFIG 0x67
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#define QLCNIC_CMD_GET_LINK_STATUS 0x68
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#define QLCNIC_CMD_SET_LED_CONFIG 0x69
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#define QLCNIC_CMD_GET_LED_CONFIG 0x6A
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#define QLCNIC_CMD_83XX_SET_DRV_VER 0x6F
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#define QLCNIC_CMD_ADD_RCV_RINGS 0x0B
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#define QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP 0x37
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#define QLCNIC_INTRPT_INTX 1
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#define QLCNIC_INTRPT_MSIX 3
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#define QLCNIC_INTRPT_ADD 1
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#define QLCNIC_INTRPT_DEL 2
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#define QLCNIC_GET_CURRENT_MAC 1
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#define QLCNIC_SET_STATION_MAC 2
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#define QLCNIC_GET_DEFAULT_MAC 3
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#define QLCNIC_GET_FAC_DEF_MAC 4
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#define QLCNIC_SET_FAC_DEF_MAC 5
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#define QLCNIC_MBX_LINK_EVENT 0x8001
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#define QLCNIC_MBX_BC_EVENT 0x8002
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#define QLCNIC_MBX_COMP_EVENT 0x8100
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#define QLCNIC_MBX_REQUEST_EVENT 0x8101
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#define QLCNIC_MBX_TIME_EXTEND_EVENT 0x8102
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#define QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT 0x8110
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#define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130
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#define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131
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struct qlcnic_mailbox_metadata {
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u32 cmd;
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u32 in_args;
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u32 out_args;
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};
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/* Mailbox ownership */
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#define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
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#define QLCNIC_SET_OWNER 1
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#define QLCNIC_CLR_OWNER 0
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#define QLCNIC_MBX_TIMEOUT 5000
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#define QLCNIC_MBX_RSP_OK 1
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#define QLCNIC_MBX_PORT_RSP_OK 0x1a
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#define QLCNIC_MBX_ASYNC_EVENT BIT_15
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/* Set HW Tx ring limit for 82xx adapter. */
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#define QLCNIC_MAX_HW_TX_RINGS 8
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#define QLCNIC_MAX_HW_VNIC_TX_RINGS 4
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#define QLCNIC_MAX_TX_RINGS 8
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#define QLCNIC_MAX_SDS_RINGS 8
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struct qlcnic_pci_info;
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struct qlcnic_info;
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struct qlcnic_cmd_args;
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struct ethtool_stats;
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struct pci_device_id;
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struct qlcnic_host_sds_ring;
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struct qlcnic_host_tx_ring;
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struct qlcnic_hardware_context;
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struct qlcnic_adapter;
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struct qlcnic_fw_dump;
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int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong, int *);
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int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
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int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int);
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int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
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int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter,
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struct net_device *netdev);
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void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *);
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void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter,
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u64 *uaddr, u16 vlan_id,
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struct qlcnic_host_tx_ring *tx_ring);
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int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *,
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struct ethtool_coalesce *);
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int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *);
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int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int);
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void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
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__be32, int);
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int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int);
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void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
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int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8);
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int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8);
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void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
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void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
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int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
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struct qlcnic_cmd_args *);
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int qlcnic_82xx_mq_intrpt(struct qlcnic_adapter *, int);
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int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *, u8);
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int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *);
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int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *,
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struct qlcnic_host_tx_ring *tx_ring, int);
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void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *);
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void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *,
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struct qlcnic_host_tx_ring *);
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int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
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int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*, u8);
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int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
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int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
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int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
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int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *,
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struct qlcnic_adapter *, u32);
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int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
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int qlcnic_82xx_get_board_info(struct qlcnic_adapter *);
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int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32);
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void qlcnic_82xx_get_func_no(struct qlcnic_adapter *);
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int qlcnic_82xx_api_lock(struct qlcnic_adapter *);
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void qlcnic_82xx_api_unlock(struct qlcnic_adapter *);
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void qlcnic_82xx_napi_enable(struct qlcnic_adapter *);
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void qlcnic_82xx_napi_disable(struct qlcnic_adapter *);
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void qlcnic_82xx_napi_del(struct qlcnic_adapter *);
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int qlcnic_82xx_shutdown(struct pci_dev *);
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int qlcnic_82xx_resume(struct qlcnic_adapter *);
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void qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8 failed);
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void qlcnic_fw_poll_work(struct work_struct *work);
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u32 qlcnic_82xx_get_saved_state(void *, u32);
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void qlcnic_82xx_set_saved_state(void *, u32, u32);
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void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
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u32 qlcnic_82xx_get_cap_size(void *, int);
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void qlcnic_82xx_set_sys_info(void *, int, u32);
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void qlcnic_82xx_store_cap_mask(void *, u32);
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#endif /* __QLCNIC_HW_H_ */
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