244 lines
7.7 KiB
C
244 lines
7.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_TXRX_H_
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#define _ICE_TXRX_H_
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#define ICE_DFLT_IRQ_WORK 256
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#define ICE_RXBUF_2048 2048
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#define ICE_MAX_CHAINED_RX_BUFS 5
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#define ICE_MAX_BUF_TXD 8
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#define ICE_MIN_TX_LEN 17
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/* The size limit for a transmit buffer in a descriptor is (16K - 1).
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* In order to align with the read requests we will align the value to
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* the nearest 4K which represents our maximum read request size.
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*/
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#define ICE_MAX_READ_REQ_SIZE 4096
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#define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
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#define ICE_MAX_DATA_PER_TXD_ALIGNED \
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(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
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#define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */
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#define ICE_MAX_TXQ_PER_TXQG 128
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/* We are assuming that the cache line is always 64 Bytes here for ice.
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* In order to make sure that is a correct assumption there is a check in probe
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* to print a warning if the read from GLPCI_CNF2 tells us that the cache line
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* size is 128 bytes. We do it this way because we do not want to read the
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* GLPCI_CNF2 register or a variable containing the value on every pass through
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* the Tx path.
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*/
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#define ICE_CACHE_LINE_BYTES 64
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#define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \
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sizeof(struct ice_tx_desc))
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#define ICE_DESCS_FOR_CTX_DESC 1
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#define ICE_DESCS_FOR_SKB_DATA_PTR 1
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/* Tx descriptors needed, worst case */
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#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
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ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
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#define ICE_DESC_UNUSED(R) \
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((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1)
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#define ICE_TX_FLAGS_TSO BIT(0)
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#define ICE_TX_FLAGS_HW_VLAN BIT(1)
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#define ICE_TX_FLAGS_SW_VLAN BIT(2)
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#define ICE_TX_FLAGS_VLAN_M 0xffff0000
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#define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000
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#define ICE_TX_FLAGS_VLAN_PR_S 29
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#define ICE_TX_FLAGS_VLAN_S 16
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#define ICE_RX_DMA_ATTR \
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(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
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struct ice_tx_buf {
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struct ice_tx_desc *next_to_watch;
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struct sk_buff *skb;
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unsigned int bytecount;
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unsigned short gso_segs;
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u32 tx_flags;
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DEFINE_DMA_UNMAP_LEN(len);
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DEFINE_DMA_UNMAP_ADDR(dma);
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};
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struct ice_tx_offload_params {
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u64 cd_qw1;
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struct ice_ring *tx_ring;
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u32 td_cmd;
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u32 td_offset;
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u32 td_l2tag1;
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u32 cd_tunnel_params;
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u16 cd_l2tag2;
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u8 header_len;
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};
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struct ice_rx_buf {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct page *page;
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unsigned int page_offset;
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u16 pagecnt_bias;
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};
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struct ice_q_stats {
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u64 pkts;
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u64 bytes;
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};
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struct ice_txq_stats {
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u64 restart_q;
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u64 tx_busy;
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u64 tx_linearize;
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int prev_pkt; /* negative if no pending Tx descriptors */
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};
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struct ice_rxq_stats {
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u64 non_eop_descs;
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u64 alloc_page_failed;
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u64 alloc_buf_failed;
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u64 page_reuse_count;
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};
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/* this enum matches hardware bits and is meant to be used by DYN_CTLN
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* registers and QINT registers or more generally anywhere in the manual
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* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
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* register but instead is a special value meaning "don't update" ITR0/1/2.
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*/
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enum ice_dyn_idx_t {
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ICE_IDX_ITR0 = 0,
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ICE_IDX_ITR1 = 1,
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ICE_IDX_ITR2 = 2,
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ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
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};
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/* Header split modes defined by DTYPE field of Rx RLAN context */
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enum ice_rx_dtype {
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ICE_RX_DTYPE_NO_SPLIT = 0,
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ICE_RX_DTYPE_HEADER_SPLIT = 1,
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ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
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};
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/* indices into GLINT_ITR registers */
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#define ICE_RX_ITR ICE_IDX_ITR0
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#define ICE_TX_ITR ICE_IDX_ITR1
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#define ICE_ITR_8K 124
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#define ICE_ITR_20K 50
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#define ICE_ITR_MAX 8160
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#define ICE_DFLT_TX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC)
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#define ICE_DFLT_RX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC)
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#define ICE_ITR_DYNAMIC 0x8000 /* used as flag for itr_setting */
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#define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC))
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#define ITR_TO_REG(setting) ((setting) & ~ICE_ITR_DYNAMIC)
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#define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */
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#define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S)
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#define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */
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#define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~ICE_ITR_MASK)
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#define ICE_ITR_ADAPTIVE_MIN_INC 0x0002
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#define ICE_ITR_ADAPTIVE_MIN_USECS 0x0002
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#define ICE_ITR_ADAPTIVE_MAX_USECS 0x00FA
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#define ICE_ITR_ADAPTIVE_LATENCY 0x8000
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#define ICE_ITR_ADAPTIVE_BULK 0x0000
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#define ICE_DFLT_INTRL 0
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#define ICE_MAX_INTRL 236
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#define ICE_WB_ON_ITR_USECS 2
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#define ICE_IN_WB_ON_ITR_MODE 255
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/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
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* setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
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* set the write-back latency to the usecs passed in.
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*/
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#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \
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((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
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GLINT_DYN_CTL_INTERVAL_M) | \
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(((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
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GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
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GLINT_DYN_CTL_WB_ON_ITR_M)
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/* Legacy or Advanced Mode Queue */
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#define ICE_TX_ADVANCED 0
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#define ICE_TX_LEGACY 1
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/* descriptor ring, associated with a VSI */
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struct ice_ring {
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/* CL1 - 1st cacheline starts here */
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struct ice_ring *next; /* pointer to next ring in q_vector */
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void *desc; /* Descriptor ring memory */
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struct device *dev; /* Used for DMA mapping */
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struct net_device *netdev; /* netdev ring maps to */
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struct ice_vsi *vsi; /* Backreference to associated VSI */
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struct ice_q_vector *q_vector; /* Backreference to associated vector */
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u8 __iomem *tail;
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union {
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struct ice_tx_buf *tx_buf;
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struct ice_rx_buf *rx_buf;
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};
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/* CL2 - 2nd cacheline starts here */
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u16 q_index; /* Queue number of ring */
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u16 q_handle; /* Queue handle per TC */
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u8 ring_active:1; /* is ring online or not */
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u16 count; /* Number of descriptors */
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u16 reg_idx; /* HW register index of the ring */
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/* used in interrupt processing */
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u16 next_to_use;
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u16 next_to_clean;
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u16 next_to_alloc;
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/* stats structs */
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struct ice_q_stats stats;
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struct u64_stats_sync syncp;
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union {
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struct ice_txq_stats tx_stats;
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struct ice_rxq_stats rx_stats;
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};
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struct rcu_head rcu; /* to avoid race on free */
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/* CLX - the below items are only accessed infrequently and should be
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* in their own cache line if possible
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*/
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dma_addr_t dma; /* physical address of ring */
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unsigned int size; /* length of descriptor ring in bytes */
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u32 txq_teid; /* Added Tx queue TEID */
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u16 rx_buf_len;
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#ifdef CONFIG_DCB
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u8 dcb_tc; /* Traffic class of ring */
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#endif /* CONFIG_DCB */
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} ____cacheline_internodealigned_in_smp;
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struct ice_ring_container {
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/* head of linked-list of rings */
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struct ice_ring *ring;
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unsigned long next_update; /* jiffies value of next queue update */
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_pkts; /* total packets processed this int */
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u16 itr_idx; /* index in the interrupt vector */
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u16 target_itr; /* value in usecs divided by the hw->itr_gran */
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u16 current_itr; /* value in usecs divided by the hw->itr_gran */
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/* high bit set means dynamic ITR, rest is used to store user
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* readable ITR value in usecs and must be converted before programming
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* to a register.
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*/
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u16 itr_setting;
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};
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/* iterator for handling rings in ring container */
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#define ice_for_each_ring(pos, head) \
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for (pos = (head).ring; pos; pos = pos->next)
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bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count);
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netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
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void ice_clean_tx_ring(struct ice_ring *tx_ring);
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void ice_clean_rx_ring(struct ice_ring *rx_ring);
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int ice_setup_tx_ring(struct ice_ring *tx_ring);
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int ice_setup_rx_ring(struct ice_ring *rx_ring);
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void ice_free_tx_ring(struct ice_ring *tx_ring);
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void ice_free_rx_ring(struct ice_ring *rx_ring);
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int ice_napi_poll(struct napi_struct *napi, int budget);
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#endif /* _ICE_TXRX_H_ */
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