382 lines
9.4 KiB
C
382 lines
9.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* aQuantia Corporation Network Driver
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* Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
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*/
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/* File aq_pci_func.c: Definition of PCI functions. */
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include "aq_main.h"
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#include "aq_nic.h"
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#include "aq_vec.h"
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#include "aq_hw.h"
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#include "aq_pci_func.h"
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#include "hw_atl/hw_atl_a0.h"
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#include "hw_atl/hw_atl_b0.h"
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#include "aq_filters.h"
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#include "aq_drvinfo.h"
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static const struct pci_device_id aq_pci_tbl[] = {
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_0001), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D100), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D107), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D108), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_D109), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC100S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC107S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC108S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC109S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC111S), },
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{ PCI_VDEVICE(AQUANTIA, AQ_DEVICE_ID_AQC112S), },
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{}
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};
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static const struct aq_board_revision_s hw_atl_boards[] = {
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{ AQ_DEVICE_ID_0001, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
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{ AQ_DEVICE_ID_D100, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc100, },
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{ AQ_DEVICE_ID_D107, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
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{ AQ_DEVICE_ID_D108, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc108, },
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{ AQ_DEVICE_ID_D109, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc109, },
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{ AQ_DEVICE_ID_0001, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_D100, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc100, },
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{ AQ_DEVICE_ID_D107, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_D108, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc108, },
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{ AQ_DEVICE_ID_D109, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc109, },
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{ AQ_DEVICE_ID_AQC100, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_AQC107, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_AQC108, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108, },
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{ AQ_DEVICE_ID_AQC109, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109, },
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{ AQ_DEVICE_ID_AQC111, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111, },
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{ AQ_DEVICE_ID_AQC112, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112, },
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{ AQ_DEVICE_ID_AQC100S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc100s, },
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{ AQ_DEVICE_ID_AQC107S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107s, },
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{ AQ_DEVICE_ID_AQC108S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108s, },
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{ AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
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{ AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
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{ AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
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};
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MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
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static int aq_pci_probe_get_hw_by_id(struct pci_dev *pdev,
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const struct aq_hw_ops **ops,
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const struct aq_hw_caps_s **caps)
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{
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int i;
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if (pdev->vendor != PCI_VENDOR_ID_AQUANTIA)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(hw_atl_boards); i++) {
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if (hw_atl_boards[i].devid == pdev->device &&
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(hw_atl_boards[i].revision == AQ_HWREV_ANY ||
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hw_atl_boards[i].revision == pdev->revision)) {
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*ops = hw_atl_boards[i].ops;
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*caps = hw_atl_boards[i].caps;
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break;
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}
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}
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if (i == ARRAY_SIZE(hw_atl_boards))
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return -EINVAL;
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return 0;
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}
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int aq_pci_func_init(struct pci_dev *pdev)
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{
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int err;
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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if (!err) {
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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}
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if (err) {
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (!err)
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err = pci_set_consistent_dma_mask(pdev,
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DMA_BIT_MASK(32));
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}
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if (err != 0) {
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err = -ENOSR;
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goto err_exit;
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}
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err = pci_request_regions(pdev, AQ_CFG_DRV_NAME "_mmio");
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if (err < 0)
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goto err_exit;
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pci_set_master(pdev);
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return 0;
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err_exit:
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return err;
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}
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int aq_pci_func_alloc_irq(struct aq_nic_s *self, unsigned int i,
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char *name, irq_handler_t irq_handler,
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void *irq_arg, cpumask_t *affinity_mask)
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{
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struct pci_dev *pdev = self->pdev;
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int err;
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if (pdev->msix_enabled || pdev->msi_enabled)
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err = request_irq(pci_irq_vector(pdev, i), irq_handler, 0,
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name, irq_arg);
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else
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err = request_irq(pci_irq_vector(pdev, i), aq_vec_isr_legacy,
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IRQF_SHARED, name, irq_arg);
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if (err >= 0) {
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self->msix_entry_mask |= (1 << i);
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if (pdev->msix_enabled && affinity_mask)
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irq_set_affinity_hint(pci_irq_vector(pdev, i),
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affinity_mask);
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}
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return err;
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}
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void aq_pci_func_free_irqs(struct aq_nic_s *self)
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{
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struct pci_dev *pdev = self->pdev;
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unsigned int i;
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void *irq_data;
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for (i = 32U; i--;) {
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if (!((1U << i) & self->msix_entry_mask))
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continue;
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if (self->aq_nic_cfg.link_irq_vec &&
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i == self->aq_nic_cfg.link_irq_vec)
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irq_data = self;
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else if (i < AQ_CFG_VECS_MAX)
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irq_data = self->aq_vec[i];
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else
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continue;
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if (pdev->msix_enabled)
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irq_set_affinity_hint(pci_irq_vector(pdev, i), NULL);
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free_irq(pci_irq_vector(pdev, i), irq_data);
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self->msix_entry_mask &= ~(1U << i);
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}
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}
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unsigned int aq_pci_func_get_irq_type(struct aq_nic_s *self)
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{
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if (self->pdev->msix_enabled)
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return AQ_HW_IRQ_MSIX;
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if (self->pdev->msi_enabled)
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return AQ_HW_IRQ_MSI;
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return AQ_HW_IRQ_LEGACY;
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}
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static void aq_pci_free_irq_vectors(struct aq_nic_s *self)
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{
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pci_free_irq_vectors(self->pdev);
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}
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static int aq_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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{
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struct aq_nic_s *self;
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int err;
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struct net_device *ndev;
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resource_size_t mmio_pa;
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u32 bar;
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u32 numvecs;
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err = pci_enable_device(pdev);
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if (err)
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return err;
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err = aq_pci_func_init(pdev);
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if (err)
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goto err_pci_func;
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ndev = aq_ndev_alloc();
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if (!ndev) {
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err = -ENOMEM;
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goto err_ndev;
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}
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self = netdev_priv(ndev);
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self->pdev = pdev;
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SET_NETDEV_DEV(ndev, &pdev->dev);
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pci_set_drvdata(pdev, self);
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mutex_init(&self->fwreq_mutex);
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err = aq_pci_probe_get_hw_by_id(pdev, &self->aq_hw_ops,
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&aq_nic_get_cfg(self)->aq_hw_caps);
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if (err)
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goto err_ioremap;
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self->aq_hw = kzalloc(sizeof(*self->aq_hw), GFP_KERNEL);
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if (!self->aq_hw) {
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err = -ENOMEM;
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goto err_ioremap;
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}
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self->aq_hw->aq_nic_cfg = aq_nic_get_cfg(self);
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for (bar = 0; bar < 4; ++bar) {
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if (IORESOURCE_MEM & pci_resource_flags(pdev, bar)) {
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resource_size_t reg_sz;
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mmio_pa = pci_resource_start(pdev, bar);
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if (mmio_pa == 0U) {
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err = -EIO;
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goto err_free_aq_hw;
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}
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reg_sz = pci_resource_len(pdev, bar);
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if ((reg_sz <= 24 /*ATL_REGS_SIZE*/)) {
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err = -EIO;
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goto err_free_aq_hw;
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}
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self->aq_hw->mmio = ioremap_nocache(mmio_pa, reg_sz);
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if (!self->aq_hw->mmio) {
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err = -EIO;
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goto err_free_aq_hw;
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}
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break;
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}
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}
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if (bar == 4) {
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err = -EIO;
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goto err_free_aq_hw;
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}
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numvecs = min((u8)AQ_CFG_VECS_DEF,
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aq_nic_get_cfg(self)->aq_hw_caps->msix_irqs);
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numvecs = min(numvecs, num_online_cpus());
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numvecs += AQ_HW_SERVICE_IRQS;
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/*enable interrupts */
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#if !AQ_CFG_FORCE_LEGACY_INT
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err = pci_alloc_irq_vectors(self->pdev, 1, numvecs,
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PCI_IRQ_MSIX | PCI_IRQ_MSI |
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PCI_IRQ_LEGACY);
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if (err < 0)
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goto err_hwinit;
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numvecs = err;
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#endif
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self->irqvecs = numvecs;
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/* net device init */
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aq_nic_cfg_start(self);
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aq_nic_ndev_init(self);
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err = aq_nic_ndev_register(self);
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if (err < 0)
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goto err_register;
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aq_drvinfo_init(ndev);
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return 0;
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err_register:
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aq_nic_free_vectors(self);
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aq_pci_free_irq_vectors(self);
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err_hwinit:
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iounmap(self->aq_hw->mmio);
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err_free_aq_hw:
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kfree(self->aq_hw);
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err_ioremap:
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free_netdev(ndev);
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err_ndev:
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pci_release_regions(pdev);
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err_pci_func:
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pci_disable_device(pdev);
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return err;
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}
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static void aq_pci_remove(struct pci_dev *pdev)
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{
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struct aq_nic_s *self = pci_get_drvdata(pdev);
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if (self->ndev) {
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aq_clear_rxnfc_all_rules(self);
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if (self->ndev->reg_state == NETREG_REGISTERED)
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unregister_netdev(self->ndev);
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aq_nic_free_vectors(self);
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aq_pci_free_irq_vectors(self);
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iounmap(self->aq_hw->mmio);
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kfree(self->aq_hw);
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pci_release_regions(pdev);
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free_netdev(self->ndev);
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}
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pci_disable_device(pdev);
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}
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static void aq_pci_shutdown(struct pci_dev *pdev)
|
||
|
|
{
|
||
|
|
struct aq_nic_s *self = pci_get_drvdata(pdev);
|
||
|
|
|
||
|
|
aq_nic_shutdown(self);
|
||
|
|
|
||
|
|
pci_disable_device(pdev);
|
||
|
|
|
||
|
|
if (system_state == SYSTEM_POWER_OFF) {
|
||
|
|
pci_wake_from_d3(pdev, false);
|
||
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static int aq_pci_suspend(struct pci_dev *pdev, pm_message_t pm_msg)
|
||
|
|
{
|
||
|
|
struct aq_nic_s *self = pci_get_drvdata(pdev);
|
||
|
|
|
||
|
|
return aq_nic_change_pm_state(self, &pm_msg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int aq_pci_resume(struct pci_dev *pdev)
|
||
|
|
{
|
||
|
|
struct aq_nic_s *self = pci_get_drvdata(pdev);
|
||
|
|
pm_message_t pm_msg = PMSG_RESTORE;
|
||
|
|
|
||
|
|
return aq_nic_change_pm_state(self, &pm_msg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pci_driver aq_pci_ops = {
|
||
|
|
.name = AQ_CFG_DRV_NAME,
|
||
|
|
.id_table = aq_pci_tbl,
|
||
|
|
.probe = aq_pci_probe,
|
||
|
|
.remove = aq_pci_remove,
|
||
|
|
.suspend = aq_pci_suspend,
|
||
|
|
.resume = aq_pci_resume,
|
||
|
|
.shutdown = aq_pci_shutdown,
|
||
|
|
};
|
||
|
|
|
||
|
|
int aq_pci_func_register_driver(void)
|
||
|
|
{
|
||
|
|
return pci_register_driver(&aq_pci_ops);
|
||
|
|
}
|
||
|
|
|
||
|
|
void aq_pci_func_unregister_driver(void)
|
||
|
|
{
|
||
|
|
pci_unregister_driver(&aq_pci_ops);
|
||
|
|
}
|
||
|
|
|