424 lines
14 KiB
C
424 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019, Vladimir Oltean <olteanv@gmail.com>
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*/
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#include "sja1105.h"
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#define SJA1105_TAS_CLKSRC_DISABLED 0
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#define SJA1105_TAS_CLKSRC_STANDALONE 1
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#define SJA1105_TAS_CLKSRC_AS6802 2
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#define SJA1105_TAS_CLKSRC_PTP 3
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#define SJA1105_TAS_MAX_DELTA BIT(19)
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#define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0)
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/* This is not a preprocessor macro because the "ns" argument may or may not be
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* s64 at caller side. This ensures it is properly type-cast before div_s64.
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*/
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static s64 ns_to_sja1105_delta(s64 ns)
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{
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return div_s64(ns, 200);
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}
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/* Lo and behold: the egress scheduler from hell.
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*
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* At the hardware level, the Time-Aware Shaper holds a global linear arrray of
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* all schedule entries for all ports. These are the Gate Control List (GCL)
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* entries, let's call them "timeslots" for short. This linear array of
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* timeslots is held in BLK_IDX_SCHEDULE.
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*
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* Then there are a maximum of 8 "execution threads" inside the switch, which
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* iterate cyclically through the "schedule". Each "cycle" has an entry point
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* and an exit point, both being timeslot indices in the schedule table. The
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* hardware calls each cycle a "subschedule".
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*
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* Subschedule (cycle) i starts when
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* ptpclkval >= ptpschtm + BLK_IDX_SCHEDULE_ENTRY_POINTS[i].delta.
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*
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* The hardware scheduler iterates BLK_IDX_SCHEDULE with a k ranging from
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* k = BLK_IDX_SCHEDULE_ENTRY_POINTS[i].address to
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* k = BLK_IDX_SCHEDULE_PARAMS.subscheind[i]
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*
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* For each schedule entry (timeslot) k, the engine executes the gate control
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* list entry for the duration of BLK_IDX_SCHEDULE[k].delta.
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*
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* +---------+
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* | | BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS
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* +---------+
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* |
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* +-----------------+
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* | .actsubsch
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* BLK_IDX_SCHEDULE_ENTRY_POINTS v
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* +-------+-------+
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* |cycle 0|cycle 1|
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* +-------+-------+
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* | | | |
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* +----------------+ | | +-------------------------------------+
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* | .subschindx | | .subschindx |
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* | | +---------------+ |
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* | .address | .address | |
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* | | | |
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* | | | |
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* | BLK_IDX_SCHEDULE v v |
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* | +-------+-------+-------+-------+-------+------+ |
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* | |entry 0|entry 1|entry 2|entry 3|entry 4|entry5| |
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* | +-------+-------+-------+-------+-------+------+ |
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* | ^ ^ ^ ^ |
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* | | | | | |
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* | +-------------------------+ | | | |
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* | | +-------------------------------+ | | |
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* | | | +-------------------+ | |
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* | | | | | |
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* | +---------------------------------------------------------------+ |
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* | |subscheind[0]<=subscheind[1]<=subscheind[2]<=...<=subscheind[7]| |
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* | +---------------------------------------------------------------+ |
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* | ^ ^ BLK_IDX_SCHEDULE_PARAMS |
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* | | | |
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* +--------+ +-------------------------------------------+
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*
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* In the above picture there are two subschedules (cycles):
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*
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* - cycle 0: iterates the schedule table from 0 to 2 (and back)
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* - cycle 1: iterates the schedule table from 3 to 5 (and back)
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*
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* All other possible execution threads must be marked as unused by making
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* their "subschedule end index" (subscheind) equal to the last valid
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* subschedule's end index (in this case 5).
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*/
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static int sja1105_init_scheduling(struct sja1105_private *priv)
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{
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struct sja1105_schedule_entry_points_entry *schedule_entry_points;
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struct sja1105_schedule_entry_points_params_entry
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*schedule_entry_points_params;
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struct sja1105_schedule_params_entry *schedule_params;
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struct sja1105_tas_data *tas_data = &priv->tas_data;
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struct sja1105_schedule_entry *schedule;
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struct sja1105_table *table;
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int schedule_start_idx;
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s64 entry_point_delta;
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int schedule_end_idx;
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int num_entries = 0;
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int num_cycles = 0;
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int cycle = 0;
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int i, k = 0;
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int port;
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/* Discard previous Schedule Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE];
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if (table->entry_count) {
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kfree(table->entries);
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table->entry_count = 0;
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}
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/* Discard previous Schedule Entry Points Parameters Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS];
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if (table->entry_count) {
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kfree(table->entries);
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table->entry_count = 0;
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}
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/* Discard previous Schedule Parameters Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_PARAMS];
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if (table->entry_count) {
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kfree(table->entries);
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table->entry_count = 0;
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}
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/* Discard previous Schedule Entry Points Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS];
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if (table->entry_count) {
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kfree(table->entries);
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table->entry_count = 0;
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}
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/* Figure out the dimensioning of the problem */
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for (port = 0; port < SJA1105_NUM_PORTS; port++) {
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if (tas_data->offload[port]) {
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num_entries += tas_data->offload[port]->num_entries;
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num_cycles++;
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}
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}
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/* Nothing to do */
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if (!num_cycles)
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return 0;
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/* Pre-allocate space in the static config tables */
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/* Schedule Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE];
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table->entries = kcalloc(num_entries, table->ops->unpacked_entry_size,
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GFP_KERNEL);
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if (!table->entries)
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return -ENOMEM;
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table->entry_count = num_entries;
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schedule = table->entries;
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/* Schedule Points Parameters Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS_PARAMS];
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table->entries = kcalloc(SJA1105_MAX_SCHEDULE_ENTRY_POINTS_PARAMS_COUNT,
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table->ops->unpacked_entry_size, GFP_KERNEL);
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if (!table->entries)
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/* Previously allocated memory will be freed automatically in
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* sja1105_static_config_free. This is true for all early
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* returns below.
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*/
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return -ENOMEM;
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table->entry_count = SJA1105_MAX_SCHEDULE_ENTRY_POINTS_PARAMS_COUNT;
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schedule_entry_points_params = table->entries;
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/* Schedule Parameters Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_PARAMS];
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table->entries = kcalloc(SJA1105_MAX_SCHEDULE_PARAMS_COUNT,
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table->ops->unpacked_entry_size, GFP_KERNEL);
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if (!table->entries)
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return -ENOMEM;
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table->entry_count = SJA1105_MAX_SCHEDULE_PARAMS_COUNT;
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schedule_params = table->entries;
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/* Schedule Entry Points Table */
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table = &priv->static_config.tables[BLK_IDX_SCHEDULE_ENTRY_POINTS];
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table->entries = kcalloc(num_cycles, table->ops->unpacked_entry_size,
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GFP_KERNEL);
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if (!table->entries)
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return -ENOMEM;
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table->entry_count = num_cycles;
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schedule_entry_points = table->entries;
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/* Finally start populating the static config tables */
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schedule_entry_points_params->clksrc = SJA1105_TAS_CLKSRC_STANDALONE;
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schedule_entry_points_params->actsubsch = num_cycles - 1;
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for (port = 0; port < SJA1105_NUM_PORTS; port++) {
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const struct tc_taprio_qopt_offload *offload;
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offload = tas_data->offload[port];
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if (!offload)
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continue;
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schedule_start_idx = k;
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schedule_end_idx = k + offload->num_entries - 1;
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/* TODO this is the base time for the port's subschedule,
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* relative to PTPSCHTM. But as we're using the standalone
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* clock source and not PTP clock as time reference, there's
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* little point in even trying to put more logic into this,
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* like preserving the phases between the subschedules of
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* different ports. We'll get all of that when switching to the
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* PTP clock source.
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*/
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entry_point_delta = 1;
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schedule_entry_points[cycle].subschindx = cycle;
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schedule_entry_points[cycle].delta = entry_point_delta;
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schedule_entry_points[cycle].address = schedule_start_idx;
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/* The subschedule end indices need to be
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* monotonically increasing.
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*/
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for (i = cycle; i < 8; i++)
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schedule_params->subscheind[i] = schedule_end_idx;
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for (i = 0; i < offload->num_entries; i++, k++) {
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s64 delta_ns = offload->entries[i].interval;
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schedule[k].delta = ns_to_sja1105_delta(delta_ns);
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schedule[k].destports = BIT(port);
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schedule[k].resmedia_en = true;
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schedule[k].resmedia = SJA1105_GATE_MASK &
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~offload->entries[i].gate_mask;
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}
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cycle++;
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}
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return 0;
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}
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/* Be there 2 port subschedules, each executing an arbitrary number of gate
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* open/close events cyclically.
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* None of those gate events must ever occur at the exact same time, otherwise
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* the switch is known to act in exotically strange ways.
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* However the hardware doesn't bother performing these integrity checks.
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* So here we are with the task of validating whether the new @admin offload
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* has any conflict with the already established TAS configuration in
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* tas_data->offload. We already know the other ports are in harmony with one
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* another, otherwise we wouldn't have saved them.
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* Each gate event executes periodically, with a period of @cycle_time and a
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* phase given by its cycle's @base_time plus its offset within the cycle
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* (which in turn is given by the length of the events prior to it).
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* There are two aspects to possible collisions:
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* - Collisions within one cycle's (actually the longest cycle's) time frame.
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* For that, we need to compare the cartesian product of each possible
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* occurrence of each event within one cycle time.
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* - Collisions in the future. Events may not collide within one cycle time,
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* but if two port schedules don't have the same periodicity (aka the cycle
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* times aren't multiples of one another), they surely will some time in the
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* future (actually they will collide an infinite amount of times).
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*/
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static bool
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sja1105_tas_check_conflicts(struct sja1105_private *priv, int port,
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const struct tc_taprio_qopt_offload *admin)
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{
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struct sja1105_tas_data *tas_data = &priv->tas_data;
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const struct tc_taprio_qopt_offload *offload;
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s64 max_cycle_time, min_cycle_time;
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s64 delta1, delta2;
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s64 rbt1, rbt2;
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s64 stop_time;
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s64 t1, t2;
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int i, j;
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s32 rem;
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offload = tas_data->offload[port];
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if (!offload)
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return false;
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/* Check if the two cycle times are multiples of one another.
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* If they aren't, then they will surely collide.
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*/
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max_cycle_time = max(offload->cycle_time, admin->cycle_time);
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min_cycle_time = min(offload->cycle_time, admin->cycle_time);
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div_s64_rem(max_cycle_time, min_cycle_time, &rem);
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if (rem)
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return true;
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/* Calculate the "reduced" base time of each of the two cycles
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* (transposed back as close to 0 as possible) by dividing to
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* the cycle time.
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*/
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div_s64_rem(offload->base_time, offload->cycle_time, &rem);
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rbt1 = rem;
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div_s64_rem(admin->base_time, admin->cycle_time, &rem);
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rbt2 = rem;
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stop_time = max_cycle_time + max(rbt1, rbt2);
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/* delta1 is the relative base time of each GCL entry within
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* the established ports' TAS config.
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*/
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for (i = 0, delta1 = 0;
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i < offload->num_entries;
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delta1 += offload->entries[i].interval, i++) {
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/* delta2 is the relative base time of each GCL entry
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* within the newly added TAS config.
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*/
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for (j = 0, delta2 = 0;
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j < admin->num_entries;
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delta2 += admin->entries[j].interval, j++) {
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/* t1 follows all possible occurrences of the
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* established ports' GCL entry i within the
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* first cycle time.
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*/
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for (t1 = rbt1 + delta1;
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t1 <= stop_time;
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t1 += offload->cycle_time) {
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/* t2 follows all possible occurrences
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* of the newly added GCL entry j
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* within the first cycle time.
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*/
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for (t2 = rbt2 + delta2;
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t2 <= stop_time;
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t2 += admin->cycle_time) {
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if (t1 == t2) {
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dev_warn(priv->ds->dev,
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"GCL entry %d collides with entry %d of port %d\n",
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j, i, port);
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return true;
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}
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}
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}
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}
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}
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return false;
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}
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int sja1105_setup_tc_taprio(struct dsa_switch *ds, int port,
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struct tc_taprio_qopt_offload *admin)
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{
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struct sja1105_private *priv = ds->priv;
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struct sja1105_tas_data *tas_data = &priv->tas_data;
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int other_port, rc, i;
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/* Can't change an already configured port (must delete qdisc first).
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* Can't delete the qdisc from an unconfigured port.
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*/
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|
|
if (!!tas_data->offload[port] == admin->enable)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
if (!admin->enable) {
|
||
|
|
taprio_offload_free(tas_data->offload[port]);
|
||
|
|
tas_data->offload[port] = NULL;
|
||
|
|
|
||
|
|
rc = sja1105_init_scheduling(priv);
|
||
|
|
if (rc < 0)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
return sja1105_static_config_reload(priv);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* The cycle time extension is the amount of time the last cycle from
|
||
|
|
* the old OPER needs to be extended in order to phase-align with the
|
||
|
|
* base time of the ADMIN when that becomes the new OPER.
|
||
|
|
* But of course our switch needs to be reset to switch-over between
|
||
|
|
* the ADMIN and the OPER configs - so much for a seamless transition.
|
||
|
|
* So don't add insult over injury and just say we don't support cycle
|
||
|
|
* time extension.
|
||
|
|
*/
|
||
|
|
if (admin->cycle_time_extension)
|
||
|
|
return -ENOTSUPP;
|
||
|
|
|
||
|
|
if (!ns_to_sja1105_delta(admin->base_time)) {
|
||
|
|
dev_err(ds->dev, "A base time of zero is not hardware-allowed\n");
|
||
|
|
return -ERANGE;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < admin->num_entries; i++) {
|
||
|
|
s64 delta_ns = admin->entries[i].interval;
|
||
|
|
s64 delta_cycles = ns_to_sja1105_delta(delta_ns);
|
||
|
|
bool too_long, too_short;
|
||
|
|
|
||
|
|
too_long = (delta_cycles >= SJA1105_TAS_MAX_DELTA);
|
||
|
|
too_short = (delta_cycles == 0);
|
||
|
|
if (too_long || too_short) {
|
||
|
|
dev_err(priv->ds->dev,
|
||
|
|
"Interval %llu too %s for GCL entry %d\n",
|
||
|
|
delta_ns, too_long ? "long" : "short", i);
|
||
|
|
return -ERANGE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (other_port = 0; other_port < SJA1105_NUM_PORTS; other_port++) {
|
||
|
|
if (other_port == port)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
if (sja1105_tas_check_conflicts(priv, other_port, admin))
|
||
|
|
return -ERANGE;
|
||
|
|
}
|
||
|
|
|
||
|
|
tas_data->offload[port] = taprio_offload_get(admin);
|
||
|
|
|
||
|
|
rc = sja1105_init_scheduling(priv);
|
||
|
|
if (rc < 0)
|
||
|
|
return rc;
|
||
|
|
|
||
|
|
return sja1105_static_config_reload(priv);
|
||
|
|
}
|
||
|
|
|
||
|
|
void sja1105_tas_setup(struct dsa_switch *ds)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
void sja1105_tas_teardown(struct dsa_switch *ds)
|
||
|
|
{
|
||
|
|
struct sja1105_private *priv = ds->priv;
|
||
|
|
struct tc_taprio_qopt_offload *offload;
|
||
|
|
int port;
|
||
|
|
|
||
|
|
for (port = 0; port < SJA1105_NUM_PORTS; port++) {
|
||
|
|
offload = priv->tas_data.offload[port];
|
||
|
|
if (!offload)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
taprio_offload_free(offload);
|
||
|
|
}
|
||
|
|
}
|