136 lines
3.0 KiB
C
136 lines
3.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2017 Free Electrons
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* Copyright (C) 2017 NextThing Co
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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*/
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#include "internals.h"
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static void samsung_nand_decode_id(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct nand_memory_organization *memorg;
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memorg = nanddev_get_memorg(&chip->base);
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/* New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44) */
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if (chip->id.len == 6 && !nand_is_slc(chip) &&
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chip->id.data[5] != 0x00) {
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u8 extid = chip->id.data[3];
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/* Get pagesize */
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memorg->pagesize = 2048 << (extid & 0x03);
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mtd->writesize = memorg->pagesize;
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extid >>= 2;
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/* Get oobsize */
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switch (((extid >> 2) & 0x4) | (extid & 0x3)) {
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case 1:
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memorg->oobsize = 128;
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break;
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case 2:
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memorg->oobsize = 218;
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break;
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case 3:
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memorg->oobsize = 400;
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break;
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case 4:
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memorg->oobsize = 436;
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break;
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case 5:
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memorg->oobsize = 512;
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break;
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case 6:
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memorg->oobsize = 640;
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break;
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default:
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/*
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* We should never reach this case, but if that
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* happens, this probably means Samsung decided to use
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* a different extended ID format, and we should find
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* a way to support it.
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*/
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WARN(1, "Invalid OOB size value");
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break;
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}
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mtd->oobsize = memorg->oobsize;
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/* Get blocksize */
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extid >>= 2;
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memorg->pages_per_eraseblock = (128 * 1024) <<
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(((extid >> 1) & 0x04) |
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(extid & 0x03)) /
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memorg->pagesize;
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mtd->erasesize = (128 * 1024) <<
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(((extid >> 1) & 0x04) | (extid & 0x03));
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/* Extract ECC requirements from 5th id byte*/
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extid = (chip->id.data[4] >> 4) & 0x07;
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if (extid < 5) {
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chip->base.eccreq.step_size = 512;
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chip->base.eccreq.strength = 1 << extid;
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} else {
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chip->base.eccreq.step_size = 1024;
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switch (extid) {
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case 5:
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chip->base.eccreq.strength = 24;
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break;
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case 6:
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chip->base.eccreq.strength = 40;
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break;
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case 7:
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chip->base.eccreq.strength = 60;
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break;
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default:
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WARN(1, "Could not decode ECC info");
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chip->base.eccreq.step_size = 0;
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}
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}
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} else {
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nand_decode_ext_id(chip);
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if (nand_is_slc(chip)) {
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switch (chip->id.data[1]) {
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/* K9F4G08U0D-S[I|C]B0(T00) */
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case 0xDC:
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chip->base.eccreq.step_size = 512;
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chip->base.eccreq.strength = 1;
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break;
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/* K9F1G08U0E 21nm chips do not support subpage write */
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case 0xF1:
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if (chip->id.len > 4 &&
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(chip->id.data[4] & GENMASK(1, 0)) == 0x1)
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chip->options |= NAND_NO_SUBPAGE_WRITE;
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break;
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default:
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break;
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}
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}
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}
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}
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static int samsung_nand_init(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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if (mtd->writesize > 512)
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chip->options |= NAND_SAMSUNG_LP_OPTIONS;
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if (!nand_is_slc(chip))
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chip->options |= NAND_BBM_LASTPAGE;
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else
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chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
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return 0;
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}
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const struct nand_manufacturer_ops samsung_nand_manuf_ops = {
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.detect = samsung_nand_decode_id,
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.init = samsung_nand_init,
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};
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