296 lines
7.2 KiB
C
296 lines
7.2 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* JZ4725B BCH controller driver
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*
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* Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
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*
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* Based on jz4780_bch.c
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include "ingenic_ecc.h"
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#define BCH_BHCR 0x0
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#define BCH_BHCSR 0x4
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#define BCH_BHCCR 0x8
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#define BCH_BHCNT 0xc
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#define BCH_BHDR 0x10
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#define BCH_BHPAR0 0x14
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#define BCH_BHERR0 0x28
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#define BCH_BHINT 0x24
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#define BCH_BHINTES 0x3c
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#define BCH_BHINTEC 0x40
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#define BCH_BHINTE 0x38
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#define BCH_BHCR_ENCE BIT(3)
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#define BCH_BHCR_BSEL BIT(2)
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#define BCH_BHCR_INIT BIT(1)
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#define BCH_BHCR_BCHE BIT(0)
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#define BCH_BHCNT_DEC_COUNT_SHIFT 16
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#define BCH_BHCNT_DEC_COUNT_MASK (0x3ff << BCH_BHCNT_DEC_COUNT_SHIFT)
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#define BCH_BHCNT_ENC_COUNT_SHIFT 0
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#define BCH_BHCNT_ENC_COUNT_MASK (0x3ff << BCH_BHCNT_ENC_COUNT_SHIFT)
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#define BCH_BHERR_INDEX0_SHIFT 0
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#define BCH_BHERR_INDEX0_MASK (0x1fff << BCH_BHERR_INDEX0_SHIFT)
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#define BCH_BHERR_INDEX1_SHIFT 16
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#define BCH_BHERR_INDEX1_MASK (0x1fff << BCH_BHERR_INDEX1_SHIFT)
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#define BCH_BHINT_ERRC_SHIFT 28
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#define BCH_BHINT_ERRC_MASK (0xf << BCH_BHINT_ERRC_SHIFT)
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#define BCH_BHINT_TERRC_SHIFT 16
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#define BCH_BHINT_TERRC_MASK (0x7f << BCH_BHINT_TERRC_SHIFT)
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#define BCH_BHINT_ALL_0 BIT(5)
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#define BCH_BHINT_ALL_F BIT(4)
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#define BCH_BHINT_DECF BIT(3)
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#define BCH_BHINT_ENCF BIT(2)
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#define BCH_BHINT_UNCOR BIT(1)
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#define BCH_BHINT_ERR BIT(0)
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/* Timeout for BCH calculation/correction. */
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#define BCH_TIMEOUT_US 100000
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static inline void jz4725b_bch_config_set(struct ingenic_ecc *bch, u32 cfg)
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{
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writel(cfg, bch->base + BCH_BHCSR);
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}
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static inline void jz4725b_bch_config_clear(struct ingenic_ecc *bch, u32 cfg)
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{
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writel(cfg, bch->base + BCH_BHCCR);
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}
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static int jz4725b_bch_reset(struct ingenic_ecc *bch,
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struct ingenic_ecc_params *params, bool calc_ecc)
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{
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u32 reg, max_value;
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/* Clear interrupt status. */
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writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
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/* Initialise and enable BCH. */
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jz4725b_bch_config_clear(bch, 0x1f);
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jz4725b_bch_config_set(bch, BCH_BHCR_BCHE);
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if (params->strength == 8)
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jz4725b_bch_config_set(bch, BCH_BHCR_BSEL);
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else
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jz4725b_bch_config_clear(bch, BCH_BHCR_BSEL);
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if (calc_ecc) /* calculate ECC from data */
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jz4725b_bch_config_set(bch, BCH_BHCR_ENCE);
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else /* correct data from ECC */
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jz4725b_bch_config_clear(bch, BCH_BHCR_ENCE);
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jz4725b_bch_config_set(bch, BCH_BHCR_INIT);
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max_value = BCH_BHCNT_ENC_COUNT_MASK >> BCH_BHCNT_ENC_COUNT_SHIFT;
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if (params->size > max_value)
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return -EINVAL;
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max_value = BCH_BHCNT_DEC_COUNT_MASK >> BCH_BHCNT_DEC_COUNT_SHIFT;
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if (params->size + params->bytes > max_value)
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return -EINVAL;
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/* Set up BCH count register. */
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reg = params->size << BCH_BHCNT_ENC_COUNT_SHIFT;
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reg |= (params->size + params->bytes) << BCH_BHCNT_DEC_COUNT_SHIFT;
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writel(reg, bch->base + BCH_BHCNT);
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return 0;
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}
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static void jz4725b_bch_disable(struct ingenic_ecc *bch)
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{
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/* Clear interrupts */
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writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
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/* Disable the hardware */
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jz4725b_bch_config_clear(bch, BCH_BHCR_BCHE);
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}
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static void jz4725b_bch_write_data(struct ingenic_ecc *bch, const u8 *buf,
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size_t size)
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{
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while (size--)
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writeb(*buf++, bch->base + BCH_BHDR);
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}
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static void jz4725b_bch_read_parity(struct ingenic_ecc *bch, u8 *buf,
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size_t size)
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{
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size_t size32 = size / sizeof(u32);
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size_t size8 = size % sizeof(u32);
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u32 *dest32;
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u8 *dest8;
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u32 val, offset = 0;
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dest32 = (u32 *)buf;
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while (size32--) {
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*dest32++ = readl_relaxed(bch->base + BCH_BHPAR0 + offset);
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offset += sizeof(u32);
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}
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dest8 = (u8 *)dest32;
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val = readl_relaxed(bch->base + BCH_BHPAR0 + offset);
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switch (size8) {
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case 3:
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dest8[2] = (val >> 16) & 0xff;
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/* fall-through */
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case 2:
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dest8[1] = (val >> 8) & 0xff;
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/* fall-through */
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case 1:
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dest8[0] = val & 0xff;
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break;
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}
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}
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static int jz4725b_bch_wait_complete(struct ingenic_ecc *bch, unsigned int irq,
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u32 *status)
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{
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u32 reg;
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int ret;
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/*
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* While we could use interrupts here and sleep until the operation
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* completes, the controller works fairly quickly (usually a few
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* microseconds) and so the overhead of sleeping until we get an
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* interrupt quite noticeably decreases performance.
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*/
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ret = readl_relaxed_poll_timeout(bch->base + BCH_BHINT, reg,
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reg & irq, 0, BCH_TIMEOUT_US);
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if (ret)
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return ret;
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if (status)
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*status = reg;
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writel(reg, bch->base + BCH_BHINT);
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return 0;
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}
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static int jz4725b_calculate(struct ingenic_ecc *bch,
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struct ingenic_ecc_params *params,
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const u8 *buf, u8 *ecc_code)
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{
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int ret;
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mutex_lock(&bch->lock);
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ret = jz4725b_bch_reset(bch, params, true);
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if (ret) {
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dev_err(bch->dev, "Unable to init BCH with given parameters\n");
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goto out_disable;
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}
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jz4725b_bch_write_data(bch, buf, params->size);
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ret = jz4725b_bch_wait_complete(bch, BCH_BHINT_ENCF, NULL);
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if (ret) {
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dev_err(bch->dev, "timed out while calculating ECC\n");
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goto out_disable;
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}
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jz4725b_bch_read_parity(bch, ecc_code, params->bytes);
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out_disable:
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jz4725b_bch_disable(bch);
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mutex_unlock(&bch->lock);
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return ret;
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}
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static int jz4725b_correct(struct ingenic_ecc *bch,
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struct ingenic_ecc_params *params,
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u8 *buf, u8 *ecc_code)
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{
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u32 reg, errors, bit;
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unsigned int i;
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int ret;
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mutex_lock(&bch->lock);
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ret = jz4725b_bch_reset(bch, params, false);
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if (ret) {
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dev_err(bch->dev, "Unable to init BCH with given parameters\n");
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goto out;
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}
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jz4725b_bch_write_data(bch, buf, params->size);
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jz4725b_bch_write_data(bch, ecc_code, params->bytes);
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ret = jz4725b_bch_wait_complete(bch, BCH_BHINT_DECF, ®);
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if (ret) {
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dev_err(bch->dev, "timed out while correcting data\n");
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goto out;
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}
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if (reg & (BCH_BHINT_ALL_F | BCH_BHINT_ALL_0)) {
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/* Data and ECC is all 0xff or 0x00 - nothing to correct */
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ret = 0;
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goto out;
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}
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if (reg & BCH_BHINT_UNCOR) {
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/* Uncorrectable ECC error */
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ret = -EBADMSG;
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goto out;
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}
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errors = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT;
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/* Correct any detected errors. */
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for (i = 0; i < errors; i++) {
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if (i & 1) {
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bit = (reg & BCH_BHERR_INDEX1_MASK) >> BCH_BHERR_INDEX1_SHIFT;
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} else {
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reg = readl(bch->base + BCH_BHERR0 + (i * 4));
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bit = (reg & BCH_BHERR_INDEX0_MASK) >> BCH_BHERR_INDEX0_SHIFT;
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}
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buf[(bit >> 3)] ^= BIT(bit & 0x7);
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}
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out:
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jz4725b_bch_disable(bch);
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mutex_unlock(&bch->lock);
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return ret;
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}
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static const struct ingenic_ecc_ops jz4725b_bch_ops = {
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.disable = jz4725b_bch_disable,
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.calculate = jz4725b_calculate,
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.correct = jz4725b_correct,
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};
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static const struct of_device_id jz4725b_bch_dt_match[] = {
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{ .compatible = "ingenic,jz4725b-bch", .data = &jz4725b_bch_ops },
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{},
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};
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MODULE_DEVICE_TABLE(of, jz4725b_bch_dt_match);
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static struct platform_driver jz4725b_bch_driver = {
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.probe = ingenic_ecc_probe,
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.driver = {
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.name = "jz4725b-bch",
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.of_match_table = jz4725b_bch_dt_match,
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},
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};
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module_platform_driver(jz4725b_bch_driver);
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_DESCRIPTION("Ingenic JZ4725B BCH controller driver");
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MODULE_LICENSE("GPL v2");
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