821 lines
20 KiB
C
821 lines
20 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/**
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* Host side test driver to test endpoint functionality
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/crc32.h>
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <uapi/linux/pcitest.h>
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#define DRV_MODULE_NAME "pci-endpoint-test"
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#define IRQ_TYPE_UNDEFINED -1
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#define IRQ_TYPE_LEGACY 0
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#define IRQ_TYPE_MSI 1
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#define IRQ_TYPE_MSIX 2
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#define PCI_ENDPOINT_TEST_MAGIC 0x0
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#define PCI_ENDPOINT_TEST_COMMAND 0x4
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#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
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#define COMMAND_RAISE_MSI_IRQ BIT(1)
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#define COMMAND_RAISE_MSIX_IRQ BIT(2)
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#define COMMAND_READ BIT(3)
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#define COMMAND_WRITE BIT(4)
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#define COMMAND_COPY BIT(5)
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#define PCI_ENDPOINT_TEST_STATUS 0x8
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#define STATUS_READ_SUCCESS BIT(0)
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#define STATUS_READ_FAIL BIT(1)
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#define STATUS_WRITE_SUCCESS BIT(2)
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#define STATUS_WRITE_FAIL BIT(3)
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#define STATUS_COPY_SUCCESS BIT(4)
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#define STATUS_COPY_FAIL BIT(5)
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#define STATUS_IRQ_RAISED BIT(6)
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#define STATUS_SRC_ADDR_INVALID BIT(7)
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#define STATUS_DST_ADDR_INVALID BIT(8)
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#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
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#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
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#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
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#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
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#define PCI_ENDPOINT_TEST_SIZE 0x1c
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#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
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#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
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#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
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#define PCI_DEVICE_ID_TI_AM654 0xb00c
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#define is_am654_pci_dev(pdev) \
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((pdev)->device == PCI_DEVICE_ID_TI_AM654)
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static DEFINE_IDA(pci_endpoint_test_ida);
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#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
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miscdev)
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static bool no_msi;
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module_param(no_msi, bool, 0444);
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MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
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static int irq_type = IRQ_TYPE_MSI;
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module_param(irq_type, int, 0444);
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MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
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enum pci_barno {
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BAR_0,
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BAR_1,
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BAR_2,
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BAR_3,
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BAR_4,
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BAR_5,
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};
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struct pci_endpoint_test {
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struct pci_dev *pdev;
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void __iomem *base;
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void __iomem *bar[6];
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struct completion irq_raised;
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int last_irq;
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int num_irqs;
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int irq_type;
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/* mutex to protect the ioctls */
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struct mutex mutex;
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struct miscdevice miscdev;
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enum pci_barno test_reg_bar;
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size_t alignment;
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};
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struct pci_endpoint_test_data {
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enum pci_barno test_reg_bar;
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size_t alignment;
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int irq_type;
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};
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static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
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u32 offset)
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{
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return readl(test->base + offset);
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}
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static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
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u32 offset, u32 value)
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{
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writel(value, test->base + offset);
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}
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static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
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int bar, int offset)
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{
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return readl(test->bar[bar] + offset);
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}
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static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
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int bar, u32 offset, u32 value)
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{
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writel(value, test->bar[bar] + offset);
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}
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static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
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{
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struct pci_endpoint_test *test = dev_id;
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u32 reg;
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reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
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if (reg & STATUS_IRQ_RAISED) {
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test->last_irq = irq;
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complete(&test->irq_raised);
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reg &= ~STATUS_IRQ_RAISED;
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}
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
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reg);
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return IRQ_HANDLED;
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}
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static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
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{
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struct pci_dev *pdev = test->pdev;
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pci_free_irq_vectors(pdev);
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test->irq_type = IRQ_TYPE_UNDEFINED;
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}
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static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
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int type)
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{
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int irq = -1;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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bool res = true;
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switch (type) {
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case IRQ_TYPE_LEGACY:
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irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
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if (irq < 0)
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dev_err(dev, "Failed to get Legacy interrupt\n");
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break;
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case IRQ_TYPE_MSI:
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irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
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if (irq < 0)
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dev_err(dev, "Failed to get MSI interrupts\n");
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break;
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case IRQ_TYPE_MSIX:
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irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
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if (irq < 0)
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dev_err(dev, "Failed to get MSI-X interrupts\n");
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break;
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default:
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dev_err(dev, "Invalid IRQ type selected\n");
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}
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if (irq < 0) {
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irq = 0;
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res = false;
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}
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test->irq_type = type;
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test->num_irqs = irq;
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return res;
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}
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static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
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{
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int i;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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for (i = 0; i < test->num_irqs; i++)
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devm_free_irq(dev, pci_irq_vector(pdev, i), test);
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test->num_irqs = 0;
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}
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static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
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{
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int i;
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int err;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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for (i = 0; i < test->num_irqs; i++) {
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err = devm_request_irq(dev, pci_irq_vector(pdev, i),
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pci_endpoint_test_irqhandler,
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IRQF_SHARED, DRV_MODULE_NAME, test);
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if (err)
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goto fail;
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}
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return true;
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fail:
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switch (irq_type) {
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case IRQ_TYPE_LEGACY:
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dev_err(dev, "Failed to request IRQ %d for Legacy\n",
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pci_irq_vector(pdev, i));
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break;
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case IRQ_TYPE_MSI:
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dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
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pci_irq_vector(pdev, i),
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i + 1);
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break;
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case IRQ_TYPE_MSIX:
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dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
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pci_irq_vector(pdev, i),
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i + 1);
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break;
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}
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return false;
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}
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static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
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enum pci_barno barno)
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{
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int j;
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u32 val;
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int size;
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struct pci_dev *pdev = test->pdev;
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if (!test->bar[barno])
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return false;
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size = pci_resource_len(pdev, barno);
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if (barno == test->test_reg_bar)
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size = 0x4;
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for (j = 0; j < size; j += 4)
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pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
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for (j = 0; j < size; j += 4) {
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val = pci_endpoint_test_bar_readl(test, barno, j);
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if (val != 0xA0A0A0A0)
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return false;
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}
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return true;
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}
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static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
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{
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u32 val;
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
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IRQ_TYPE_LEGACY);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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COMMAND_RAISE_LEGACY_IRQ);
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val = wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000));
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if (!val)
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return false;
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return true;
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}
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static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
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u16 msi_num, bool msix)
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{
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u32 val;
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struct pci_dev *pdev = test->pdev;
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
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msix == false ? IRQ_TYPE_MSI :
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IRQ_TYPE_MSIX);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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msix == false ? COMMAND_RAISE_MSI_IRQ :
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COMMAND_RAISE_MSIX_IRQ);
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val = wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000));
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if (!val)
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return false;
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if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
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return true;
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return false;
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}
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static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size)
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{
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bool ret = false;
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void *src_addr;
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void *dst_addr;
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dma_addr_t src_phys_addr;
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dma_addr_t dst_phys_addr;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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void *orig_src_addr;
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dma_addr_t orig_src_phys_addr;
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void *orig_dst_addr;
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dma_addr_t orig_dst_phys_addr;
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size_t offset;
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size_t alignment = test->alignment;
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int irq_type = test->irq_type;
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u32 src_crc32;
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u32 dst_crc32;
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if (size > SIZE_MAX - alignment)
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goto err;
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if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
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dev_err(dev, "Invalid IRQ type option\n");
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goto err;
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}
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orig_src_addr = dma_alloc_coherent(dev, size + alignment,
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&orig_src_phys_addr, GFP_KERNEL);
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if (!orig_src_addr) {
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dev_err(dev, "Failed to allocate source buffer\n");
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ret = false;
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goto err;
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}
|
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|
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if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
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src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
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offset = src_phys_addr - orig_src_phys_addr;
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src_addr = orig_src_addr + offset;
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} else {
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src_phys_addr = orig_src_phys_addr;
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src_addr = orig_src_addr;
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}
|
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|
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
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lower_32_bits(src_phys_addr));
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|
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
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upper_32_bits(src_phys_addr));
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|
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get_random_bytes(src_addr, size);
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src_crc32 = crc32_le(~0, src_addr, size);
|
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|
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orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
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&orig_dst_phys_addr, GFP_KERNEL);
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if (!orig_dst_addr) {
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dev_err(dev, "Failed to allocate destination address\n");
|
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|
ret = false;
|
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|
goto err_orig_src_addr;
|
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|
}
|
||
|
|
||
|
if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
|
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dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
|
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|
offset = dst_phys_addr - orig_dst_phys_addr;
|
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|
dst_addr = orig_dst_addr + offset;
|
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|
} else {
|
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|
dst_phys_addr = orig_dst_phys_addr;
|
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|
dst_addr = orig_dst_addr;
|
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|
}
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
|
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|
lower_32_bits(dst_phys_addr));
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
|
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|
upper_32_bits(dst_phys_addr));
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
|
||
|
size);
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
|
||
|
COMMAND_COPY);
|
||
|
|
||
|
wait_for_completion(&test->irq_raised);
|
||
|
|
||
|
dst_crc32 = crc32_le(~0, dst_addr, size);
|
||
|
if (dst_crc32 == src_crc32)
|
||
|
ret = true;
|
||
|
|
||
|
dma_free_coherent(dev, size + alignment, orig_dst_addr,
|
||
|
orig_dst_phys_addr);
|
||
|
|
||
|
err_orig_src_addr:
|
||
|
dma_free_coherent(dev, size + alignment, orig_src_addr,
|
||
|
orig_src_phys_addr);
|
||
|
|
||
|
err:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size)
|
||
|
{
|
||
|
bool ret = false;
|
||
|
u32 reg;
|
||
|
void *addr;
|
||
|
dma_addr_t phys_addr;
|
||
|
struct pci_dev *pdev = test->pdev;
|
||
|
struct device *dev = &pdev->dev;
|
||
|
void *orig_addr;
|
||
|
dma_addr_t orig_phys_addr;
|
||
|
size_t offset;
|
||
|
size_t alignment = test->alignment;
|
||
|
int irq_type = test->irq_type;
|
||
|
u32 crc32;
|
||
|
|
||
|
if (size > SIZE_MAX - alignment)
|
||
|
goto err;
|
||
|
|
||
|
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
|
||
|
dev_err(dev, "Invalid IRQ type option\n");
|
||
|
goto err;
|
||
|
}
|
||
|
|
||
|
orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
|
||
|
GFP_KERNEL);
|
||
|
if (!orig_addr) {
|
||
|
dev_err(dev, "Failed to allocate address\n");
|
||
|
ret = false;
|
||
|
goto err;
|
||
|
}
|
||
|
|
||
|
if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
|
||
|
phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
|
||
|
offset = phys_addr - orig_phys_addr;
|
||
|
addr = orig_addr + offset;
|
||
|
} else {
|
||
|
phys_addr = orig_phys_addr;
|
||
|
addr = orig_addr;
|
||
|
}
|
||
|
|
||
|
get_random_bytes(addr, size);
|
||
|
|
||
|
crc32 = crc32_le(~0, addr, size);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
|
||
|
crc32);
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
|
||
|
lower_32_bits(phys_addr));
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
|
||
|
upper_32_bits(phys_addr));
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
|
||
|
COMMAND_READ);
|
||
|
|
||
|
wait_for_completion(&test->irq_raised);
|
||
|
|
||
|
reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
|
||
|
if (reg & STATUS_READ_SUCCESS)
|
||
|
ret = true;
|
||
|
|
||
|
dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
|
||
|
|
||
|
err:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size)
|
||
|
{
|
||
|
bool ret = false;
|
||
|
void *addr;
|
||
|
dma_addr_t phys_addr;
|
||
|
struct pci_dev *pdev = test->pdev;
|
||
|
struct device *dev = &pdev->dev;
|
||
|
void *orig_addr;
|
||
|
dma_addr_t orig_phys_addr;
|
||
|
size_t offset;
|
||
|
size_t alignment = test->alignment;
|
||
|
int irq_type = test->irq_type;
|
||
|
u32 crc32;
|
||
|
|
||
|
if (size > SIZE_MAX - alignment)
|
||
|
goto err;
|
||
|
|
||
|
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
|
||
|
dev_err(dev, "Invalid IRQ type option\n");
|
||
|
goto err;
|
||
|
}
|
||
|
|
||
|
orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
|
||
|
GFP_KERNEL);
|
||
|
if (!orig_addr) {
|
||
|
dev_err(dev, "Failed to allocate destination address\n");
|
||
|
ret = false;
|
||
|
goto err;
|
||
|
}
|
||
|
|
||
|
if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
|
||
|
phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
|
||
|
offset = phys_addr - orig_phys_addr;
|
||
|
addr = orig_addr + offset;
|
||
|
} else {
|
||
|
phys_addr = orig_phys_addr;
|
||
|
addr = orig_addr;
|
||
|
}
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
|
||
|
lower_32_bits(phys_addr));
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
|
||
|
upper_32_bits(phys_addr));
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
|
||
|
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
|
||
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
|
||
|
COMMAND_WRITE);
|
||
|
|
||
|
wait_for_completion(&test->irq_raised);
|
||
|
|
||
|
crc32 = crc32_le(~0, addr, size);
|
||
|
if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
|
||
|
ret = true;
|
||
|
|
||
|
dma_free_coherent(dev, size + alignment, orig_addr, orig_phys_addr);
|
||
|
err:
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
|
||
|
int req_irq_type)
|
||
|
{
|
||
|
struct pci_dev *pdev = test->pdev;
|
||
|
struct device *dev = &pdev->dev;
|
||
|
|
||
|
if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
|
||
|
dev_err(dev, "Invalid IRQ type option\n");
|
||
|
return false;
|
||
|
}
|
||
|
|
||
|
if (test->irq_type == req_irq_type)
|
||
|
return true;
|
||
|
|
||
|
pci_endpoint_test_release_irq(test);
|
||
|
pci_endpoint_test_free_irq_vectors(test);
|
||
|
|
||
|
if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
|
||
|
goto err;
|
||
|
|
||
|
if (!pci_endpoint_test_request_irq(test))
|
||
|
goto err;
|
||
|
|
||
|
return true;
|
||
|
|
||
|
err:
|
||
|
pci_endpoint_test_free_irq_vectors(test);
|
||
|
return false;
|
||
|
}
|
||
|
|
||
|
static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
|
||
|
unsigned long arg)
|
||
|
{
|
||
|
int ret = -EINVAL;
|
||
|
enum pci_barno bar;
|
||
|
struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
|
||
|
struct pci_dev *pdev = test->pdev;
|
||
|
|
||
|
mutex_lock(&test->mutex);
|
||
|
switch (cmd) {
|
||
|
case PCITEST_BAR:
|
||
|
bar = arg;
|
||
|
if (bar < 0 || bar > 5)
|
||
|
goto ret;
|
||
|
if (is_am654_pci_dev(pdev) && bar == BAR_0)
|
||
|
goto ret;
|
||
|
ret = pci_endpoint_test_bar(test, bar);
|
||
|
break;
|
||
|
case PCITEST_LEGACY_IRQ:
|
||
|
ret = pci_endpoint_test_legacy_irq(test);
|
||
|
break;
|
||
|
case PCITEST_MSI:
|
||
|
case PCITEST_MSIX:
|
||
|
ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
|
||
|
break;
|
||
|
case PCITEST_WRITE:
|
||
|
ret = pci_endpoint_test_write(test, arg);
|
||
|
break;
|
||
|
case PCITEST_READ:
|
||
|
ret = pci_endpoint_test_read(test, arg);
|
||
|
break;
|
||
|
case PCITEST_COPY:
|
||
|
ret = pci_endpoint_test_copy(test, arg);
|
||
|
break;
|
||
|
case PCITEST_SET_IRQTYPE:
|
||
|
ret = pci_endpoint_test_set_irq(test, arg);
|
||
|
break;
|
||
|
case PCITEST_GET_IRQTYPE:
|
||
|
ret = irq_type;
|
||
|
break;
|
||
|
}
|
||
|
|
||
|
ret:
|
||
|
mutex_unlock(&test->mutex);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static const struct file_operations pci_endpoint_test_fops = {
|
||
|
.owner = THIS_MODULE,
|
||
|
.unlocked_ioctl = pci_endpoint_test_ioctl,
|
||
|
};
|
||
|
|
||
|
static int pci_endpoint_test_probe(struct pci_dev *pdev,
|
||
|
const struct pci_device_id *ent)
|
||
|
{
|
||
|
int err;
|
||
|
int id;
|
||
|
char name[24];
|
||
|
enum pci_barno bar;
|
||
|
void __iomem *base;
|
||
|
struct device *dev = &pdev->dev;
|
||
|
struct pci_endpoint_test *test;
|
||
|
struct pci_endpoint_test_data *data;
|
||
|
enum pci_barno test_reg_bar = BAR_0;
|
||
|
struct miscdevice *misc_device;
|
||
|
|
||
|
if (pci_is_bridge(pdev))
|
||
|
return -ENODEV;
|
||
|
|
||
|
test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
|
||
|
if (!test)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
test->test_reg_bar = 0;
|
||
|
test->alignment = 0;
|
||
|
test->pdev = pdev;
|
||
|
test->irq_type = IRQ_TYPE_UNDEFINED;
|
||
|
|
||
|
if (no_msi)
|
||
|
irq_type = IRQ_TYPE_LEGACY;
|
||
|
|
||
|
data = (struct pci_endpoint_test_data *)ent->driver_data;
|
||
|
if (data) {
|
||
|
test_reg_bar = data->test_reg_bar;
|
||
|
test->test_reg_bar = test_reg_bar;
|
||
|
test->alignment = data->alignment;
|
||
|
irq_type = data->irq_type;
|
||
|
}
|
||
|
|
||
|
init_completion(&test->irq_raised);
|
||
|
mutex_init(&test->mutex);
|
||
|
|
||
|
err = pci_enable_device(pdev);
|
||
|
if (err) {
|
||
|
dev_err(dev, "Cannot enable PCI device\n");
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
err = pci_request_regions(pdev, DRV_MODULE_NAME);
|
||
|
if (err) {
|
||
|
dev_err(dev, "Cannot obtain PCI resources\n");
|
||
|
goto err_disable_pdev;
|
||
|
}
|
||
|
|
||
|
pci_set_master(pdev);
|
||
|
|
||
|
if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
|
||
|
goto err_disable_irq;
|
||
|
|
||
|
if (!pci_endpoint_test_request_irq(test))
|
||
|
goto err_disable_irq;
|
||
|
|
||
|
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
||
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
|
||
|
base = pci_ioremap_bar(pdev, bar);
|
||
|
if (!base) {
|
||
|
dev_err(dev, "Failed to read BAR%d\n", bar);
|
||
|
WARN_ON(bar == test_reg_bar);
|
||
|
}
|
||
|
test->bar[bar] = base;
|
||
|
}
|
||
|
}
|
||
|
|
||
|
test->base = test->bar[test_reg_bar];
|
||
|
if (!test->base) {
|
||
|
err = -ENOMEM;
|
||
|
dev_err(dev, "Cannot perform PCI test without BAR%d\n",
|
||
|
test_reg_bar);
|
||
|
goto err_iounmap;
|
||
|
}
|
||
|
|
||
|
pci_set_drvdata(pdev, test);
|
||
|
|
||
|
id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
|
||
|
if (id < 0) {
|
||
|
err = id;
|
||
|
dev_err(dev, "Unable to get id\n");
|
||
|
goto err_iounmap;
|
||
|
}
|
||
|
|
||
|
snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
|
||
|
misc_device = &test->miscdev;
|
||
|
misc_device->minor = MISC_DYNAMIC_MINOR;
|
||
|
misc_device->name = kstrdup(name, GFP_KERNEL);
|
||
|
if (!misc_device->name) {
|
||
|
err = -ENOMEM;
|
||
|
goto err_ida_remove;
|
||
|
}
|
||
|
misc_device->fops = &pci_endpoint_test_fops,
|
||
|
|
||
|
err = misc_register(misc_device);
|
||
|
if (err) {
|
||
|
dev_err(dev, "Failed to register device\n");
|
||
|
goto err_kfree_name;
|
||
|
}
|
||
|
|
||
|
return 0;
|
||
|
|
||
|
err_kfree_name:
|
||
|
kfree(misc_device->name);
|
||
|
|
||
|
err_ida_remove:
|
||
|
ida_simple_remove(&pci_endpoint_test_ida, id);
|
||
|
|
||
|
err_iounmap:
|
||
|
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
||
|
if (test->bar[bar])
|
||
|
pci_iounmap(pdev, test->bar[bar]);
|
||
|
}
|
||
|
pci_endpoint_test_release_irq(test);
|
||
|
|
||
|
err_disable_irq:
|
||
|
pci_endpoint_test_free_irq_vectors(test);
|
||
|
pci_release_regions(pdev);
|
||
|
|
||
|
err_disable_pdev:
|
||
|
pci_disable_device(pdev);
|
||
|
|
||
|
return err;
|
||
|
}
|
||
|
|
||
|
static void pci_endpoint_test_remove(struct pci_dev *pdev)
|
||
|
{
|
||
|
int id;
|
||
|
enum pci_barno bar;
|
||
|
struct pci_endpoint_test *test = pci_get_drvdata(pdev);
|
||
|
struct miscdevice *misc_device = &test->miscdev;
|
||
|
|
||
|
if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
|
||
|
return;
|
||
|
if (id < 0)
|
||
|
return;
|
||
|
|
||
|
misc_deregister(&test->miscdev);
|
||
|
kfree(misc_device->name);
|
||
|
ida_simple_remove(&pci_endpoint_test_ida, id);
|
||
|
for (bar = BAR_0; bar <= BAR_5; bar++) {
|
||
|
if (test->bar[bar])
|
||
|
pci_iounmap(pdev, test->bar[bar]);
|
||
|
}
|
||
|
|
||
|
pci_endpoint_test_release_irq(test);
|
||
|
pci_endpoint_test_free_irq_vectors(test);
|
||
|
|
||
|
pci_release_regions(pdev);
|
||
|
pci_disable_device(pdev);
|
||
|
}
|
||
|
|
||
|
static const struct pci_endpoint_test_data am654_data = {
|
||
|
.test_reg_bar = BAR_2,
|
||
|
.alignment = SZ_64K,
|
||
|
.irq_type = IRQ_TYPE_MSI,
|
||
|
};
|
||
|
|
||
|
static const struct pci_device_id pci_endpoint_test_tbl[] = {
|
||
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
|
||
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
|
||
|
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
|
||
|
{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
|
||
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
|
||
|
.driver_data = (kernel_ulong_t)&am654_data
|
||
|
},
|
||
|
{ }
|
||
|
};
|
||
|
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
|
||
|
|
||
|
static struct pci_driver pci_endpoint_test_driver = {
|
||
|
.name = DRV_MODULE_NAME,
|
||
|
.id_table = pci_endpoint_test_tbl,
|
||
|
.probe = pci_endpoint_test_probe,
|
||
|
.remove = pci_endpoint_test_remove,
|
||
|
};
|
||
|
module_pci_driver(pci_endpoint_test_driver);
|
||
|
|
||
|
MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
|
||
|
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
||
|
MODULE_LICENSE("GPL v2");
|