322 lines
8.1 KiB
C
322 lines
8.1 KiB
C
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/*
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* Memory controller driver for ARM PrimeCell PL172
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* PrimeCell MultiPort Memory Controller (PL172)
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*
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* Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
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*
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* Based on:
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* TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/amba/bus.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/time.h>
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#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * n)
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#define MPMC_STATIC_CFG_MW_8BIT 0x0
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#define MPMC_STATIC_CFG_MW_16BIT 0x1
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#define MPMC_STATIC_CFG_MW_32BIT 0x2
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#define MPMC_STATIC_CFG_PM BIT(3)
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#define MPMC_STATIC_CFG_PC BIT(6)
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#define MPMC_STATIC_CFG_PB BIT(7)
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#define MPMC_STATIC_CFG_EW BIT(8)
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#define MPMC_STATIC_CFG_B BIT(19)
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#define MPMC_STATIC_CFG_P BIT(20)
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#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * n)
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#define MPMC_STATIC_WAIT_WEN_MAX 0x0f
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#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * n)
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#define MPMC_STATIC_WAIT_OEN_MAX 0x0f
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#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * n)
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#define MPMC_STATIC_WAIT_RD_MAX 0x1f
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#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * n)
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#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f
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#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * n)
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#define MPMC_STATIC_WAIT_WR_MAX 0x1f
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#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * n)
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#define MPMC_STATIC_WAIT_TURN_MAX 0x0f
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/* Maximum number of static chip selects */
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#define PL172_MAX_CS 4
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struct pl172_data {
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void __iomem *base;
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unsigned long rate;
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struct clk *clk;
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};
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static int pl172_timing_prop(struct amba_device *adev,
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const struct device_node *np, const char *name,
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u32 reg_offset, u32 max, int start)
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{
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struct pl172_data *pl172 = amba_get_drvdata(adev);
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int cycles;
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u32 val;
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if (!of_property_read_u32(np, name, &val)) {
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cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
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if (cycles < 0) {
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cycles = 0;
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} else if (cycles > max) {
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dev_err(&adev->dev, "%s timing too tight\n", name);
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return -EINVAL;
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}
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writel(cycles, pl172->base + reg_offset);
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}
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dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
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readl(pl172->base + reg_offset));
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return 0;
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}
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static int pl172_setup_static(struct amba_device *adev,
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struct device_node *np, u32 cs)
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{
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struct pl172_data *pl172 = amba_get_drvdata(adev);
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u32 cfg;
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int ret;
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/* MPMC static memory configuration */
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if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
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if (cfg == 8) {
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cfg = MPMC_STATIC_CFG_MW_8BIT;
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} else if (cfg == 16) {
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cfg = MPMC_STATIC_CFG_MW_16BIT;
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} else if (cfg == 32) {
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cfg = MPMC_STATIC_CFG_MW_32BIT;
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} else {
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dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
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return -EINVAL;
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}
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} else {
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dev_err(&adev->dev, "memory-width property required\n");
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return -EINVAL;
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}
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if (of_property_read_bool(np, "mpmc,async-page-mode"))
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cfg |= MPMC_STATIC_CFG_PM;
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if (of_property_read_bool(np, "mpmc,cs-active-high"))
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cfg |= MPMC_STATIC_CFG_PC;
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if (of_property_read_bool(np, "mpmc,byte-lane-low"))
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cfg |= MPMC_STATIC_CFG_PB;
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if (of_property_read_bool(np, "mpmc,extended-wait"))
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cfg |= MPMC_STATIC_CFG_EW;
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if (amba_part(adev) == 0x172 &&
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of_property_read_bool(np, "mpmc,buffer-enable"))
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cfg |= MPMC_STATIC_CFG_B;
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if (of_property_read_bool(np, "mpmc,write-protect"))
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cfg |= MPMC_STATIC_CFG_P;
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writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
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dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
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/* MPMC static memory timing */
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ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
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MPMC_STATIC_WAIT_WEN(cs),
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MPMC_STATIC_WAIT_WEN_MAX, 1);
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if (ret)
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goto fail;
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ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
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MPMC_STATIC_WAIT_OEN(cs),
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MPMC_STATIC_WAIT_OEN_MAX, 0);
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if (ret)
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goto fail;
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ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
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MPMC_STATIC_WAIT_RD(cs),
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MPMC_STATIC_WAIT_RD_MAX, 1);
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if (ret)
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goto fail;
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ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
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MPMC_STATIC_WAIT_PAGE(cs),
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MPMC_STATIC_WAIT_PAGE_MAX, 1);
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if (ret)
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goto fail;
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ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
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MPMC_STATIC_WAIT_WR(cs),
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MPMC_STATIC_WAIT_WR_MAX, 2);
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if (ret)
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goto fail;
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ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
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MPMC_STATIC_WAIT_TURN(cs),
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MPMC_STATIC_WAIT_TURN_MAX, 1);
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if (ret)
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goto fail;
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return 0;
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fail:
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dev_err(&adev->dev, "failed to configure cs%u\n", cs);
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return ret;
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}
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static int pl172_parse_cs_config(struct amba_device *adev,
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struct device_node *np)
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{
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u32 cs;
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if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
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if (cs >= PL172_MAX_CS) {
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dev_err(&adev->dev, "cs%u invalid\n", cs);
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return -EINVAL;
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}
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return pl172_setup_static(adev, np, cs);
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}
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dev_err(&adev->dev, "cs property required\n");
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return -EINVAL;
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}
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static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
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static const char * const pl175_revisions[] = {"r1"};
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static const char * const pl176_revisions[] = {"r0"};
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static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
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{
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struct device_node *child_np, *np = adev->dev.of_node;
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struct device *dev = &adev->dev;
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static const char *rev = "?";
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struct pl172_data *pl172;
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int ret;
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if (amba_part(adev) == 0x172) {
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if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
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rev = pl172_revisions[amba_rev(adev)];
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} else if (amba_part(adev) == 0x175) {
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if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
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rev = pl175_revisions[amba_rev(adev)];
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} else if (amba_part(adev) == 0x176) {
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if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
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rev = pl176_revisions[amba_rev(adev)];
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}
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dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
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pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
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if (!pl172)
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return -ENOMEM;
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pl172->clk = devm_clk_get(dev, "mpmcclk");
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if (IS_ERR(pl172->clk)) {
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dev_err(dev, "no mpmcclk provided clock\n");
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return PTR_ERR(pl172->clk);
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}
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ret = clk_prepare_enable(pl172->clk);
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if (ret) {
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dev_err(dev, "unable to mpmcclk enable clock\n");
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return ret;
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}
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pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
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if (!pl172->rate) {
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dev_err(dev, "unable to get mpmcclk clock rate\n");
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ret = -EINVAL;
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goto err_clk_enable;
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}
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ret = amba_request_regions(adev, NULL);
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if (ret) {
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dev_err(dev, "unable to request AMBA regions\n");
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goto err_clk_enable;
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}
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pl172->base = devm_ioremap(dev, adev->res.start,
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resource_size(&adev->res));
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if (!pl172->base) {
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dev_err(dev, "ioremap failed\n");
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ret = -ENOMEM;
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goto err_no_ioremap;
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}
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amba_set_drvdata(adev, pl172);
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/*
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* Loop through each child node, which represent a chip select, and
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* configure parameters and timing. If successful; populate devices
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* under that node.
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*/
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for_each_available_child_of_node(np, child_np) {
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ret = pl172_parse_cs_config(adev, child_np);
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if (ret)
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continue;
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of_platform_populate(child_np, NULL, NULL, dev);
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}
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return 0;
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err_no_ioremap:
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amba_release_regions(adev);
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err_clk_enable:
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clk_disable_unprepare(pl172->clk);
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return ret;
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}
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static int pl172_remove(struct amba_device *adev)
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{
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struct pl172_data *pl172 = amba_get_drvdata(adev);
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clk_disable_unprepare(pl172->clk);
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amba_release_regions(adev);
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return 0;
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}
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static const struct amba_id pl172_ids[] = {
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/* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
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{
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.id = 0x07041172,
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.mask = 0x3f0fffff,
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},
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/* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
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{
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.id = 0x07041175,
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.mask = 0x3f0fffff,
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},
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/* PrimeCell MPMC PL176 */
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{
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.id = 0x89041176,
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.mask = 0xff0fffff,
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},
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{ 0, 0 },
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};
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MODULE_DEVICE_TABLE(amba, pl172_ids);
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static struct amba_driver pl172_driver = {
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.drv = {
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.name = "memory-pl172",
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},
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.probe = pl172_probe,
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.remove = pl172_remove,
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.id_table = pl172_ids,
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};
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module_amba_driver(pl172_driver);
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MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
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MODULE_DESCRIPTION("PL172 Memory Controller Driver");
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MODULE_LICENSE("GPL v2");
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