94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* drivers/media/platform/s5p-cec/regs-cec.h
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*
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* Copyright (c) 2010 Samsung Electronics
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* http://www.samsung.com/
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*
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* register header file for Samsung TVOUT driver
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*/
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#ifndef __EXYNOS_REGS__H
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#define __EXYNOS_REGS__H
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/*
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* Register part
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*/
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#define S5P_CEC_STATUS_0 (0x0000)
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#define S5P_CEC_STATUS_1 (0x0004)
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#define S5P_CEC_STATUS_2 (0x0008)
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#define S5P_CEC_STATUS_3 (0x000C)
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#define S5P_CEC_IRQ_MASK (0x0010)
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#define S5P_CEC_IRQ_CLEAR (0x0014)
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#define S5P_CEC_LOGIC_ADDR (0x0020)
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#define S5P_CEC_DIVISOR_0 (0x0030)
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#define S5P_CEC_DIVISOR_1 (0x0034)
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#define S5P_CEC_DIVISOR_2 (0x0038)
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#define S5P_CEC_DIVISOR_3 (0x003C)
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#define S5P_CEC_TX_CTRL (0x0040)
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#define S5P_CEC_TX_BYTES (0x0044)
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#define S5P_CEC_TX_STAT0 (0x0060)
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#define S5P_CEC_TX_STAT1 (0x0064)
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#define S5P_CEC_TX_BUFF0 (0x0080)
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#define S5P_CEC_TX_BUFF1 (0x0084)
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#define S5P_CEC_TX_BUFF2 (0x0088)
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#define S5P_CEC_TX_BUFF3 (0x008C)
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#define S5P_CEC_TX_BUFF4 (0x0090)
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#define S5P_CEC_TX_BUFF5 (0x0094)
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#define S5P_CEC_TX_BUFF6 (0x0098)
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#define S5P_CEC_TX_BUFF7 (0x009C)
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#define S5P_CEC_TX_BUFF8 (0x00A0)
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#define S5P_CEC_TX_BUFF9 (0x00A4)
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#define S5P_CEC_TX_BUFF10 (0x00A8)
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#define S5P_CEC_TX_BUFF11 (0x00AC)
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#define S5P_CEC_TX_BUFF12 (0x00B0)
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#define S5P_CEC_TX_BUFF13 (0x00B4)
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#define S5P_CEC_TX_BUFF14 (0x00B8)
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#define S5P_CEC_TX_BUFF15 (0x00BC)
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#define S5P_CEC_RX_CTRL (0x00C0)
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#define S5P_CEC_RX_STAT0 (0x00E0)
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#define S5P_CEC_RX_STAT1 (0x00E4)
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#define S5P_CEC_RX_BUFF0 (0x0100)
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#define S5P_CEC_RX_BUFF1 (0x0104)
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#define S5P_CEC_RX_BUFF2 (0x0108)
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#define S5P_CEC_RX_BUFF3 (0x010C)
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#define S5P_CEC_RX_BUFF4 (0x0110)
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#define S5P_CEC_RX_BUFF5 (0x0114)
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#define S5P_CEC_RX_BUFF6 (0x0118)
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#define S5P_CEC_RX_BUFF7 (0x011C)
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#define S5P_CEC_RX_BUFF8 (0x0120)
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#define S5P_CEC_RX_BUFF9 (0x0124)
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#define S5P_CEC_RX_BUFF10 (0x0128)
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#define S5P_CEC_RX_BUFF11 (0x012C)
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#define S5P_CEC_RX_BUFF12 (0x0130)
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#define S5P_CEC_RX_BUFF13 (0x0134)
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#define S5P_CEC_RX_BUFF14 (0x0138)
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#define S5P_CEC_RX_BUFF15 (0x013C)
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#define S5P_CEC_RX_FILTER_CTRL (0x0180)
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#define S5P_CEC_RX_FILTER_TH (0x0184)
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/*
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* Bit definition part
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*/
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#define S5P_CEC_IRQ_TX_DONE (1<<0)
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#define S5P_CEC_IRQ_TX_ERROR (1<<1)
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#define S5P_CEC_IRQ_RX_DONE (1<<4)
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#define S5P_CEC_IRQ_RX_ERROR (1<<5)
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#define S5P_CEC_TX_CTRL_START (1<<0)
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#define S5P_CEC_TX_CTRL_BCAST (1<<1)
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#define S5P_CEC_TX_CTRL_RETRY (0x04<<4)
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#define S5P_CEC_TX_CTRL_RESET (1<<7)
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#define S5P_CEC_RX_CTRL_ENABLE (1<<0)
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#define S5P_CEC_RX_CTRL_RESET (1<<7)
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#define S5P_CEC_LOGIC_ADDR_MASK (0xF)
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/* PMU Registers for PHY */
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#define EXYNOS_HDMI_PHY_CONTROL 0x700
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#endif /* __EXYNOS_REGS__H */
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