382 lines
10 KiB
C
382 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Spreadtrum Communications Inc.
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* Copyright (C) 2018 Linaro Ltd.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/* EIC registers definition */
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#define SPRD_PMIC_EIC_DATA 0x0
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#define SPRD_PMIC_EIC_DMSK 0x4
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#define SPRD_PMIC_EIC_IEV 0x14
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#define SPRD_PMIC_EIC_IE 0x18
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#define SPRD_PMIC_EIC_RIS 0x1c
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#define SPRD_PMIC_EIC_MIS 0x20
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#define SPRD_PMIC_EIC_IC 0x24
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#define SPRD_PMIC_EIC_TRIG 0x28
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#define SPRD_PMIC_EIC_CTRL0 0x40
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/*
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* The PMIC EIC controller only has one bank, and each bank now can contain
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* 16 EICs.
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*/
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#define SPRD_PMIC_EIC_PER_BANK_NR 16
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#define SPRD_PMIC_EIC_NR SPRD_PMIC_EIC_PER_BANK_NR
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#define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0)
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#define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
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#define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0)
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/*
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* These registers are modified under the irq bus lock and cached to avoid
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* unnecessary writes in bus_sync_unlock.
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*/
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enum {
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REG_IEV,
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REG_IE,
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REG_TRIG,
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CACHE_NR_REGS
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};
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/**
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* struct sprd_pmic_eic - PMIC EIC controller
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* @chip: the gpio_chip structure.
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* @intc: the irq_chip structure.
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* @regmap: the regmap from the parent device.
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* @offset: the EIC controller's offset address of the PMIC.
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* @reg: the array to cache the EIC registers.
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* @buslock: for bus lock/sync and unlock.
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* @irq: the interrupt number of the PMIC EIC conteroller.
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*/
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struct sprd_pmic_eic {
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struct gpio_chip chip;
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struct irq_chip intc;
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struct regmap *map;
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u32 offset;
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u8 reg[CACHE_NR_REGS];
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struct mutex buslock;
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int irq;
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};
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static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
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u16 reg, unsigned int val)
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{
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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u32 shift = SPRD_PMIC_EIC_BIT(offset);
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regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
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BIT(shift), val << shift);
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}
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static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
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u16 reg)
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{
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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u32 value;
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int ret;
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ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
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if (ret)
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return ret;
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return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
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}
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static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
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{
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
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return 0;
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}
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static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
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{
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
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}
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static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
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{
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return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
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}
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static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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/* EICs are always input, nothing need to do here. */
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return 0;
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}
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static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
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int value)
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{
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/* EICs are always input, nothing need to do here. */
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}
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static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
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unsigned int offset,
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unsigned int debounce)
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{
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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u32 reg, value;
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int ret;
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reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
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ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
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if (ret)
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return ret;
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value &= ~SPRD_PMIC_EIC_DBNC_MASK;
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value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
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return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
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}
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static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
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unsigned long config)
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{
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unsigned long param = pinconf_to_config_param(config);
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u32 arg = pinconf_to_config_argument(config);
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if (param == PIN_CONFIG_INPUT_DEBOUNCE)
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return sprd_pmic_eic_set_debounce(chip, offset, arg);
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return -ENOTSUPP;
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}
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static void sprd_pmic_eic_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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pmic_eic->reg[REG_IE] = 0;
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pmic_eic->reg[REG_TRIG] = 0;
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}
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static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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pmic_eic->reg[REG_IE] = 1;
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pmic_eic->reg[REG_TRIG] = 1;
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}
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static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
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unsigned int flow_type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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switch (flow_type) {
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case IRQ_TYPE_LEVEL_HIGH:
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pmic_eic->reg[REG_IEV] = 1;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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pmic_eic->reg[REG_IEV] = 0;
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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/*
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* Will set the trigger level according to current EIC level
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* in irq_bus_sync_unlock() interface, so here nothing to do.
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*/
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static void sprd_pmic_eic_bus_lock(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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mutex_lock(&pmic_eic->buslock);
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}
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static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
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u32 trigger = irqd_get_trigger_type(data);
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u32 offset = irqd_to_hwirq(data);
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int state;
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/* Set irq type */
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if (trigger & IRQ_TYPE_EDGE_BOTH) {
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state = sprd_pmic_eic_get(chip, offset);
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if (state)
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
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else
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
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} else {
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
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pmic_eic->reg[REG_IEV]);
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}
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/* Set irq unmask */
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
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pmic_eic->reg[REG_IE]);
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/* Generate trigger start pulse for debounce EIC */
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
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pmic_eic->reg[REG_TRIG]);
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mutex_unlock(&pmic_eic->buslock);
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}
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static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
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unsigned int irq, unsigned int offset)
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{
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u32 trigger = irq_get_trigger_type(irq);
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int state, post_state;
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if (!(trigger & IRQ_TYPE_EDGE_BOTH))
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return;
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state = sprd_pmic_eic_get(chip, offset);
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retry:
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if (state)
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
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else
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
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post_state = sprd_pmic_eic_get(chip, offset);
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if (state != post_state) {
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dev_warn(chip->parent, "PMIC EIC level was changed.\n");
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state = post_state;
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goto retry;
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}
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/* Set irq unmask */
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
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/* Generate trigger start pulse for debounce EIC */
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sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
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}
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static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
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{
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struct sprd_pmic_eic *pmic_eic = data;
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struct gpio_chip *chip = &pmic_eic->chip;
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unsigned long status;
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u32 n, girq, val;
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int ret;
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ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
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&val);
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if (ret)
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return IRQ_RETVAL(ret);
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status = val & SPRD_PMIC_EIC_DATA_MASK;
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for_each_set_bit(n, &status, chip->ngpio) {
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/* Clear the interrupt */
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sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
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girq = irq_find_mapping(chip->irq.domain, n);
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handle_nested_irq(girq);
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/*
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* The PMIC EIC can only support level trigger, so we can
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* toggle the level trigger to emulate the edge trigger.
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*/
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sprd_pmic_eic_toggle_trigger(chip, girq, n);
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}
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return IRQ_HANDLED;
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}
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static int sprd_pmic_eic_probe(struct platform_device *pdev)
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{
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struct gpio_irq_chip *irq;
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struct sprd_pmic_eic *pmic_eic;
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int ret;
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pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
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if (!pmic_eic)
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return -ENOMEM;
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mutex_init(&pmic_eic->buslock);
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pmic_eic->irq = platform_get_irq(pdev, 0);
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if (pmic_eic->irq < 0)
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return pmic_eic->irq;
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pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
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if (!pmic_eic->map)
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return -ENODEV;
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ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
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if (ret) {
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dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
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return ret;
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}
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ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
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sprd_pmic_eic_irq_handler,
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IRQF_ONESHOT | IRQF_NO_SUSPEND,
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dev_name(&pdev->dev), pmic_eic);
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if (ret) {
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dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
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return ret;
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}
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pmic_eic->chip.label = dev_name(&pdev->dev);
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pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
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pmic_eic->chip.base = -1;
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pmic_eic->chip.parent = &pdev->dev;
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pmic_eic->chip.of_node = pdev->dev.of_node;
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pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
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pmic_eic->chip.request = sprd_pmic_eic_request;
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pmic_eic->chip.free = sprd_pmic_eic_free;
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pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
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pmic_eic->chip.set = sprd_pmic_eic_set;
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pmic_eic->chip.get = sprd_pmic_eic_get;
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pmic_eic->intc.name = dev_name(&pdev->dev);
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pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
|
||
|
|
pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
|
||
|
|
pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
|
||
|
|
pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
|
||
|
|
pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
|
||
|
|
pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
|
||
|
|
|
||
|
|
irq = &pmic_eic->chip.irq;
|
||
|
|
irq->chip = &pmic_eic->intc;
|
||
|
|
irq->threaded = true;
|
||
|
|
|
||
|
|
ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, pmic_eic);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id sprd_pmic_eic_of_match[] = {
|
||
|
|
{ .compatible = "sprd,sc2731-eic", },
|
||
|
|
{ /* end of list */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver sprd_pmic_eic_driver = {
|
||
|
|
.probe = sprd_pmic_eic_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "sprd-pmic-eic",
|
||
|
|
.of_match_table = sprd_pmic_eic_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(sprd_pmic_eic_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|